On-chip bus thermal analysis and optimisation

F. Wang, M. De Bole, X. Wu, Y. Xie, Vijaykrishnan Narayanan, Mary Jane Irwin

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


As technology scales, increasing clock rates, decreasing interconnect pitch and the introduction of low-k dielectrics have made self-heating of the global interconnects an important issue in VLSI design. Further, high bus temperatures have had a negative impact on the delay and reliability of on-chip interconnects. Energy and thermal models are used to characterise the effects of self-heating on the temperature of on-chip interconnects. The results obtained show that self-heating of on-chip buses contribute significantly to the temperature of the bus, which increases as technology scales, motivating the need to find solutions to mitigate this effect. The theoretical analysis performed shows that spreading switching activities among all bus lines can effectively reduce the peak temperature of the on-chip bus. Based on this observation, a thermal spreading encoding scheme for on-chip buses is proposed to tackle the thermal issue. The results obtained show that this approach is very effective in reducing the transient peak temperature among bus lines, with much less overhead compared with other low-power encoding schemes. This technique can then be combined with low-power encoding schemes to further reduce the on-chip bus temperature.

Original languageEnglish (US)
Pages (from-to)590-599
Number of pages10
JournalIET Computers and Digital Techniques
Issue number5
StatePublished - Sep 25 2007

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


Dive into the research topics of 'On-chip bus thermal analysis and optimisation'. Together they form a unique fingerprint.

Cite this