On-chip bus thermal analysis and optimization

Feng Wang, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

As technology scales, increasing clock rates, decreasing interconnect pitch, and the introduction of low-k dielectrics have made self-heating of the global interconnects an important issue in VLSI design. In this paper, we study the self-heating of on-chip buses and show that the thermal impact due to self-heating of onchip buses increases as technology scales, thus motivating the need of finding solutions to mitigate this effect. Based on the theoretical analysis, we propose an irredundant bus encoding scheme for on-chip buses to tackle the thermal issue. Simulation results show that our encoding scheme is very efficient to reduce the on-chip bus temperature rise over substrate temperature, with much less overhead compared to other low power encoding schemes.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE'06
StatePublished - Dec 1 2006
EventDesign, Automation and Test in Europe, DATE'06 - Munich, Germany
Duration: Mar 6 2006Mar 10 2006

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
Volume1
ISSN (Print)1530-1591

Other

OtherDesign, Automation and Test in Europe, DATE'06
CountryGermany
CityMunich
Period3/6/063/10/06

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Wang, F., Xie, Y., Narayanan, V., & Irwin, M. J. (2006). On-chip bus thermal analysis and optimization. In Proceedings - Design, Automation and Test in Europe, DATE'06 [1657008] (Proceedings -Design, Automation and Test in Europe, DATE; Vol. 1).