On-chip memory management for embedded MpSoC architectures based on data compression

O. Ozturk, M. Kandemir, M. J. Irwin, S. Tosun

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

One must be very careful in utilizing the available on-chip memory space in embedded MpSoC architectures, which may be very challenging due to data sharing among processors. This paper proposes and evaluates an on-chip memory space management strategy based on data compression. The proposed strategy first uses a compiler analysis that reveals the order in which different data blocks will be required by the application. After that, it builds an integer linear programming based representation of the on-chip memory space management problem, and solves it using a publicly-available integer linear programming tool. The solution gives the optimum order in which data blocks should be compressed and decompressed to minimize execution cycles or energy consumption under an on-chip memory capacity limit.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference, 2005 SOCC
EditorsD. Ha, R. Krishnamurthy, S. Kim, A. Marshall
Pages175-178
Number of pages4
StatePublished - Dec 1 2005
Event2005 IEEE International SOC Conference - Herndon, VA, United States
Duration: Sep 25 2005Sep 28 2005

Publication series

NameProceedings - IEEE International SOC Conference

Other

Other2005 IEEE International SOC Conference
CountryUnited States
CityHerndon, VA
Period9/25/059/28/05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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