On-chip memory management for embedded MpSoC architectures based on data compression

O. Ozturk, Mahmut Kandemir, Mary Jane Irwin, S. Tosun

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

One must be very careful in utilizing the available on-chip memory space in embedded MpSoC architectures, which may be very challenging due to data sharing among processors. This paper proposes and evaluates an on-chip memory space management strategy based on data compression. The proposed strategy first uses a compiler analysis that reveals the order in which different data blocks will be required by the application. After that, it builds an integer linear programming based representation of the on-chip memory space management problem, and solves it using a publicly-available integer linear programming tool. The solution gives the optimum order in which data blocks should be compressed and decompressed to minimize execution cycles or energy consumption under an on-chip memory capacity limit.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference, 2005 SOCC
EditorsD. Ha, R. Krishnamurthy, S. Kim, A. Marshall
Pages175-178
Number of pages4
StatePublished - Dec 1 2005
Event2005 IEEE International SOC Conference - Herndon, VA, United States
Duration: Sep 25 2005Sep 28 2005

Publication series

NameProceedings - IEEE International SOC Conference

Other

Other2005 IEEE International SOC Conference
CountryUnited States
CityHerndon, VA
Period9/25/059/28/05

Fingerprint

Data compression
Data storage equipment
Linear programming
Energy utilization

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Ozturk, O., Kandemir, M., Irwin, M. J., & Tosun, S. (2005). On-chip memory management for embedded MpSoC architectures based on data compression. In D. Ha, R. Krishnamurthy, S. Kim, & A. Marshall (Eds.), Proceedings - IEEE International SOC Conference, 2005 SOCC (pp. 175-178). [TB2.3] (Proceedings - IEEE International SOC Conference).
Ozturk, O. ; Kandemir, Mahmut ; Irwin, Mary Jane ; Tosun, S. / On-chip memory management for embedded MpSoC architectures based on data compression. Proceedings - IEEE International SOC Conference, 2005 SOCC. editor / D. Ha ; R. Krishnamurthy ; S. Kim ; A. Marshall. 2005. pp. 175-178 (Proceedings - IEEE International SOC Conference).
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abstract = "One must be very careful in utilizing the available on-chip memory space in embedded MpSoC architectures, which may be very challenging due to data sharing among processors. This paper proposes and evaluates an on-chip memory space management strategy based on data compression. The proposed strategy first uses a compiler analysis that reveals the order in which different data blocks will be required by the application. After that, it builds an integer linear programming based representation of the on-chip memory space management problem, and solves it using a publicly-available integer linear programming tool. The solution gives the optimum order in which data blocks should be compressed and decompressed to minimize execution cycles or energy consumption under an on-chip memory capacity limit.",
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Ozturk, O, Kandemir, M, Irwin, MJ & Tosun, S 2005, On-chip memory management for embedded MpSoC architectures based on data compression. in D Ha, R Krishnamurthy, S Kim & A Marshall (eds), Proceedings - IEEE International SOC Conference, 2005 SOCC., TB2.3, Proceedings - IEEE International SOC Conference, pp. 175-178, 2005 IEEE International SOC Conference, Herndon, VA, United States, 9/25/05.

On-chip memory management for embedded MpSoC architectures based on data compression. / Ozturk, O.; Kandemir, Mahmut; Irwin, Mary Jane; Tosun, S.

Proceedings - IEEE International SOC Conference, 2005 SOCC. ed. / D. Ha; R. Krishnamurthy; S. Kim; A. Marshall. 2005. p. 175-178 TB2.3 (Proceedings - IEEE International SOC Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - One must be very careful in utilizing the available on-chip memory space in embedded MpSoC architectures, which may be very challenging due to data sharing among processors. This paper proposes and evaluates an on-chip memory space management strategy based on data compression. The proposed strategy first uses a compiler analysis that reveals the order in which different data blocks will be required by the application. After that, it builds an integer linear programming based representation of the on-chip memory space management problem, and solves it using a publicly-available integer linear programming tool. The solution gives the optimum order in which data blocks should be compressed and decompressed to minimize execution cycles or energy consumption under an on-chip memory capacity limit.

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Ozturk O, Kandemir M, Irwin MJ, Tosun S. On-chip memory management for embedded MpSoC architectures based on data compression. In Ha D, Krishnamurthy R, Kim S, Marshall A, editors, Proceedings - IEEE International SOC Conference, 2005 SOCC. 2005. p. 175-178. TB2.3. (Proceedings - IEEE International SOC Conference).