On-line prediction of multiprocessor memory access patterns

M. F. Sakr, C. L. Giles, S. P. Levitan, B. G. Horne, D. M. Maggini, D. M. Chiarulli

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

A neural network based technique is introduced which hides the control latency of reconfigurable interconnection networks (INs) in shared memory multiprocessors. Such INs require complex control mechanisms to reconfigure the IN on demand, in order to satisfy processor-memory accesses. Hiding the control latency seen by each access improves multiprocessor performance significantly. The new technique hides control latency by employing a time-delay neural network (TDNN) as a prediction technique that learns the current processor-memory access patterns and predicts the need to reconfigure the IN. Training and prediction of the TDNN is performed on-line. Based on three experiments, the TDNN is able to learn repetitive patterns and predict the need to reconfigure the IN thus, effectively hiding control latency of processor-memory accesses.

Original languageEnglish (US)
Title of host publicationIEEE International Conference on Neural Networks - Conference Proceedings
PublisherIEEE
Pages1564-1569
Number of pages6
Volume3
StatePublished - 1996
EventProceedings of the 1996 IEEE International Conference on Neural Networks, ICNN. Part 1 (of 4) - Washington, DC, USA
Duration: Jun 3 1996Jun 6 1996

Other

OtherProceedings of the 1996 IEEE International Conference on Neural Networks, ICNN. Part 1 (of 4)
CityWashington, DC, USA
Period6/3/966/6/96

All Science Journal Classification (ASJC) codes

  • Software

Fingerprint Dive into the research topics of 'On-line prediction of multiprocessor memory access patterns'. Together they form a unique fingerprint.

Cite this