On load latency in low-power caches

S. Kim, N. Vijaykrishnan, M. J. Irwin, L. K. John

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of nondeterminism in cache access latency. Due to this additional latency, instructions speculatively issued and dependent on a non-deterministic load must be re-executed. Our experiments show that there is a large performance degradation and associated energy wastage due to these effects of instruction re-execution. To address this problem, we propose an early cache set resolution scheme. It is based on the observation that the displacement values used for address generation are generally small. Our experimental evaluation shows that this technique is quite effective in mitigating this problem.

Original languageEnglish (US)
Title of host publicationISLPED 2003 - Proceedings of the 2003 International Symposium on Low Power Electronics and Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages258-261
Number of pages4
ISBN (Electronic)158113682X
DOIs
StatePublished - 2003
Event2003 International Symposium on Low Power Electronics and Design, ISLPED 2003 - Seoul, Korea, Republic of
Duration: Aug 25 2003Aug 27 2003

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
Volume2003-January
ISSN (Print)1533-4678

Conference

Conference2003 International Symposium on Low Power Electronics and Design, ISLPED 2003
CountryKorea, Republic of
CitySeoul
Period8/25/038/27/03

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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