@inproceedings{546dd55912c64aa0889829bec8b6d234,
title = "On load latency in low-power caches",
abstract = "Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of nondeterminism in cache access latency. Due to this additional latency, instructions speculatively issued and dependent on a non-deterministic load must be re-executed. Our experiments show that there is a large performance degradation and associated energy wastage due to these effects of instruction re-execution. To address this problem, we propose an early cache set resolution scheme. It is based on the observation that the displacement values used for address generation are generally small. Our experimental evaluation shows that this technique is quite effective in mitigating this problem.",
author = "S. Kim and N. Vijaykrishnan and Irwin, {M. J.} and John, {L. K.}",
note = "Publisher Copyright: {\textcopyright} 2003 ACM.; 2003 International Symposium on Low Power Electronics and Design, ISLPED 2003 ; Conference date: 25-08-2003 Through 27-08-2003",
year = "2003",
doi = "10.1109/LPE.2003.1231872",
language = "English (US)",
series = "Proceedings of the International Symposium on Low Power Electronics and Design",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "258--261",
booktitle = "ISLPED 2003 - Proceedings of the 2003 International Symposium on Low Power Electronics and Design",
address = "United States",
}