On Load Latency in Low-Power Caches

Soontae Kim, N. Vijaykrishnan, M. J. Irwin, L. K. John

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations


Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of non-determinism in cache access latency. Due to this additional latency, instructions speculatively issued and dependent on a non-deterministic load must be re-executed. Our experiments show that there is a large performance degradation and associated energy wastage due to these effects of instruction re-execution. To address this problem, we propose an early cache set resolution scheme. It is based on the observation that the displacement values used for address generation are generally small. Our experimental evaluation shows that this technique is quite effective in mitigating this problem.

Original languageEnglish (US)
Pages (from-to)258-261
Number of pages4
JournalProceedings of the International Symposium on Low Power Electronics and Design
StatePublished - 2003
EventProceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03) - Seoul, Korea, Republic of
Duration: Aug 25 2003Aug 27 2003

All Science Journal Classification (ASJC) codes

  • Engineering(all)


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