On reconfigurable single-electron transistor arrays synthesis using reordering techniques

Chang En Chiang, Li Fu Tang, Chun Yao Wang, Ching Yi Huang, Yung Chih Chen, Suman Datta, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

Power consumption has become one of the primary challenges in meeting Moore's law. Fortunately, Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra low power consumption during operation. An automated mapping approach for the SET architecture has been proposed recently for facilitating design realization. In this paper, we propose an enhanced approach consisting of variable reordering, product term reordering, and mapping constraint relaxation techniques to minimizing the area of mapped SET arrays. The experimental results show that our enhanced approach, on average, saves 40% in area and 17% in mapping time compared to the state-of-the-art approach for a set of MCNC and IWLS 2005 benchmarks.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE 2013
Pages1807-1812
Number of pages6
StatePublished - Oct 21 2013
Event16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 - Grenoble, France
Duration: Mar 18 2013Mar 22 2013

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013
CountryFrance
CityGrenoble
Period3/18/133/22/13

Fingerprint

Single electron transistors
Electric power utilization
Temperature

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Chiang, C. E., Tang, L. F., Wang, C. Y., Huang, C. Y., Chen, Y. C., Datta, S., & Narayanan, V. (2013). On reconfigurable single-electron transistor arrays synthesis using reordering techniques. In Proceedings - Design, Automation and Test in Europe, DATE 2013 (pp. 1807-1812). [6513808] (Proceedings -Design, Automation and Test in Europe, DATE).
Chiang, Chang En ; Tang, Li Fu ; Wang, Chun Yao ; Huang, Ching Yi ; Chen, Yung Chih ; Datta, Suman ; Narayanan, Vijaykrishnan. / On reconfigurable single-electron transistor arrays synthesis using reordering techniques. Proceedings - Design, Automation and Test in Europe, DATE 2013. 2013. pp. 1807-1812 (Proceedings -Design, Automation and Test in Europe, DATE).
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Chiang, CE, Tang, LF, Wang, CY, Huang, CY, Chen, YC, Datta, S & Narayanan, V 2013, On reconfigurable single-electron transistor arrays synthesis using reordering techniques. in Proceedings - Design, Automation and Test in Europe, DATE 2013., 6513808, Proceedings -Design, Automation and Test in Europe, DATE, pp. 1807-1812, 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013, Grenoble, France, 3/18/13.

On reconfigurable single-electron transistor arrays synthesis using reordering techniques. / Chiang, Chang En; Tang, Li Fu; Wang, Chun Yao; Huang, Ching Yi; Chen, Yung Chih; Datta, Suman; Narayanan, Vijaykrishnan.

Proceedings - Design, Automation and Test in Europe, DATE 2013. 2013. p. 1807-1812 6513808 (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chiang CE, Tang LF, Wang CY, Huang CY, Chen YC, Datta S et al. On reconfigurable single-electron transistor arrays synthesis using reordering techniques. In Proceedings - Design, Automation and Test in Europe, DATE 2013. 2013. p. 1807-1812. 6513808. (Proceedings -Design, Automation and Test in Europe, DATE).