On the effects of process variation in network-on-chip architectures

Chrysostomos Nicopoulos, Suresh Srinivasan, Aditya Yanamandra, Dongkook Park, Vijaykrishnan Narayanan, Chita R. Das, Mary J. Irwin

Research output: Contribution to journalArticle

40 Scopus citations

Abstract

The advent of diminutive technology feature sizes has led to escalating transistor densities. Burgeoning transistor counts are casting a dark shadow on modern chip design: global interconnect delays are dominating gate delays and affecting overall system performance. Networks-on-Chip (NoC) are viewed as a viable solution to this problem because of their scalability and optimized electrical properties. However, on-chip routers are susceptible to another artifact of deep submicron technology, Process Variation (PV). PV is a consequence of manufacturing imperfections, which may lead to degraded performance and even erroneous behavior. In this work, we present the first comprehensive evaluation of NoC susceptibility to PV effects, and we propose an array of architectural improvements in the form of a new router designcalled SturdiSwitchto increase resiliency to these effects. Through extensive reengineering of critical components, SturdiSwitch provides increased immunity to PV while improving performance and increasing area and power efficiency.

Original languageEnglish (US)
Article number4663075
Pages (from-to)240-254
Number of pages15
JournalIEEE Transactions on Dependable and Secure Computing
Volume7
Issue number3
DOIs
StatePublished - Jan 1 2010

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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