On the parasitic gate capacitance of small-geometry MOSFETs

Mamidala Jagadesh Kumar; Vivek Venkataraman; Sumeet Kumar Gupta

doi:10.1109/TED.2005.850630

On the parasitic gate capacitance of small-geometry MOSFETs

Mamidala Jagadesh Kumar, Vivek Venkataraman, Sumeet Kumar Gupta

Electrical Engineering

Research output: Contribution to journal › Article

6 Scopus citations

Abstract

In most cases, accurate and simple models are required to predict the detrimental effect of the parasitic capacitances in aggressively scaled-down MOSFETs. Correct models for C_top and C_bottom should be employed since each of these capacitances, if considered independently, will have a different effect on the device performance.

Original language	English (US)
Pages (from-to)	1676-1677
Number of pages	2
Journal	IEEE Transactions on Electron Devices
Volume	52
Issue number	7
DOIs	https://doi.org/10.1109/TED.2005.850630
Publication status	Published - Jul 1 2005

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All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Kumar, M. J., Venkataraman, V., & Gupta, S. K. (2005). On the parasitic gate capacitance of small-geometry MOSFETs. IEEE Transactions on Electron Devices, 52(7), 1676-1677. https://doi.org/10.1109/TED.2005.850630

@article{8cb125491af74e89a788915039719e7f,

title = "On the parasitic gate capacitance of small-geometry MOSFETs",

abstract = "In most cases, accurate and simple models are required to predict the detrimental effect of the parasitic capacitances in aggressively scaled-down MOSFETs. Correct models for Ctop and Cbottom should be employed since each of these capacitances, if considered independently, will have a different effect on the device performance.",

author = "Kumar, {Mamidala Jagadesh} and Vivek Venkataraman and Gupta, {Sumeet Kumar}",

year = "2005",

month = "7",

day = "1",

doi = "10.1109/TED.2005.850630",

language = "English (US)",

volume = "52",

pages = "1676--1677",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "7",

}

TY - JOUR

T1 - On the parasitic gate capacitance of small-geometry MOSFETs

AU - Kumar, Mamidala Jagadesh

AU - Venkataraman, Vivek

AU - Gupta, Sumeet Kumar

PY - 2005/7/1

Y1 - 2005/7/1

N2 - In most cases, accurate and simple models are required to predict the detrimental effect of the parasitic capacitances in aggressively scaled-down MOSFETs. Correct models for Ctop and Cbottom should be employed since each of these capacitances, if considered independently, will have a different effect on the device performance.

AB - In most cases, accurate and simple models are required to predict the detrimental effect of the parasitic capacitances in aggressively scaled-down MOSFETs. Correct models for Ctop and Cbottom should be employed since each of these capacitances, if considered independently, will have a different effect on the device performance.

UR - http://www.scopus.com/inward/record.url?scp=23944459384&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=23944459384&partnerID=8YFLogxK

U2 - 10.1109/TED.2005.850630

DO - 10.1109/TED.2005.850630

M3 - Article

AN - SCOPUS:23944459384

VL - 52

SP - 1676

EP - 1677

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 7

ER -

Access to Document

10.1109/TED.2005.850630