On the parasitic gate capacitance of small-geometry MOSFETs

Mamidala Jagadesh Kumar, Vivek Venkataraman, Sumeet Kumar Gupta

Research output: Contribution to journalArticle

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Abstract

In most cases, accurate and simple models are required to predict the detrimental effect of the parasitic capacitances in aggressively scaled-down MOSFETs. Correct models for Ctop and Cbottom should be employed since each of these capacitances, if considered independently, will have a different effect on the device performance.

Original languageEnglish (US)
Pages (from-to)1676-1677
Number of pages2
JournalIEEE Transactions on Electron Devices
Volume52
Issue number7
DOIs
Publication statusPublished - Jul 1 2005

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All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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