Online detection and diagnosis of multiple configuration upsets in LUTs of SRAM-based FPGAs

E. Syam Sundar Reddy, Vikram Chandrasekhar, M. Sashikanth, V. Kamakoti, N. Vijaykrishnan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

This paper proposes a new CLB architecture for FPGAs and associated online testing and reconfiguration techniques that detect configuration upsets in the LUTs of SRAMbased FPGAs and correct them using partial reconfiguration. These configuration upsets may either be Single Event Upsets(SEUs) or even Multiple Configuration Upsets. Any error in a CLB is detected with a latency of just 16 clock cycles and the errors are diagnosed by propagating them to a single output port by a chain-like shift register. The proposed CLB architectures requires only 2 additional SRAM configuration bits per LUT for a Xilinx Virtex II architecture. This is extremely low when compared to the 16 additional SRAM configuration bits required by CLB architectures used to implement standard DWC techniques for detecting configuration upsets in LUTs.

Original languageEnglish (US)
Title of host publicationProceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Pages172a
DOIs
StatePublished - Dec 1 2005
Event19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 - Denver, CO, United States
Duration: Apr 4 2005Apr 8 2005

Publication series

NameProceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Volume2005

Other

Other19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
CountryUnited States
CityDenver, CO
Period4/4/054/8/05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Reddy, E. S. S., Chandrasekhar, V., Sashikanth, M., Kamakoti, V., & Vijaykrishnan, N. (2005). Online detection and diagnosis of multiple configuration upsets in LUTs of SRAM-based FPGAs. In Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 (pp. 172a). [1420045] (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005; Vol. 2005). https://doi.org/10.1109/IPDPS.2005.308