Optimizing bus energy consumption of on-chip multiprocessors using frequent values

Research output: Contribution to journalConference article

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Abstract

Chip multiprocessors (CMP) are a convenient way of leveraging from the technological trends to build high-end and embedded systems that are performance and power efficient, while exhibiting attractive properties such as scalability, reliability and ease of design. However, the on-chip interconnect for moving the data between the processors, and between the processors and memory subsystem, plays a crucial role in CMP design. This paper presents a novel approach to optimizing its power by exploiting the value locality in data transfers between processors. A communicating value cache (CVC) is proposed to reduce the number of bits transferred on the interconnect, and simulation results with several parallel applications show significant energy savings with this mechanism. Results show that the importance of our proposal will become even more significant in the future.

Original languageEnglish (US)
Pages (from-to)129-142
Number of pages14
JournalJournal of Systems Architecture
Volume52
Issue number2
DOIs
StatePublished - Feb 1 2006
EventParallel, Distributed and Network-Based Processing -
Duration: Feb 11 2004Feb 13 2004

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All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture

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