Optimizing code parallelization through a constraint network based approach

Ozcan Ozturk, Guilin Chen, Mahmut Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Increasing employment of chip multiprocessors in embedded computing platforms requires a fresh look at conventional code parallelization schemes. In particular, any compiler-based parallelization scheme for chip multiprocessors should account for the fact that interprocessor communication is cheaper than off-chip memory accesses in these architectures. Based on this observation, this paper proposes a constraint network based approach to code parallelization for chip multiprocessors. Constraint networks have proven to be a useful mechanism for modeling and solving computationally intensive tasks in artificial intelligence. They operate by expressing a problem as a set of variables, variable domains and constraints and define a search procedure that tries to satisfy the constraints (an acceptable subset of them) by assigning values to variables from their specified domains. This paper demonstrates that it is possible to use a constraint network based formulation for the problem of code parallelization for chip multiprocessors. Our experimental evaluation shows that not only a constraint network based approach is feasible for our problem but also highly desirable since it outperforms all other parallelization schemes tested in our experiments.

Original languageEnglish (US)
Title of host publication2006 43rd ACM/IEEE Design Automation Conference, DAC'06
Number of pages6
StatePublished - Dec 1 2006

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering


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