Optimizing power and performance for reliable on-chip networks

Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

We propose novel techniques to minimize the power and performance penalties in protecting the NoC against soft errors, while giving desired reliability guarantees. Some applications have inherent error tolerance which can be exploited to save power, by turning off the error correction mechanisms for a fraction of the total time without trading off reliability. To further increase the power savings, we bound the vulnerability of a router by throttling the traffic into the router. In order to minimize the throughput loss due to throttling, we propose dividing the die into domains and using multiple vulnerability bounds across these domains. We explore both static and dynamic selection of vulnerability bounds. We find that for applications with an error tolerance of 10% of the raw error rate, the dynamic multiple vulnerability bound scheme can save up to 44% of power expended for error correction at a marginal network throughput loss of 3%.

Original languageEnglish (US)
Title of host publication2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Pages431-436
Number of pages6
DOIs
Publication statusPublished - Apr 28 2010
Event2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan, Province of China
Duration: Jan 18 2010Jan 21 2010

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
CountryTaiwan, Province of China
CityTaipei
Period1/18/101/21/10

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All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Yanamandra, A., Eachempati, S., Soundararajan, N., Narayanan, V., Irwin, M. J., & Krishnan, R. (2010). Optimizing power and performance for reliable on-chip networks. In 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 (pp. 431-436). [5419844] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2010.5419844