The authors overview a CAD system under development at Pennsylvania State University which will allow fast and near-optimal implementation of a restricted class of VLSI architectures. The architectures are hierarchical mesh extensions of systolic meshes. Applications are primarily in the signal processing domain. The primitive components, at the lowest level in the mesh hierarchy, are one of the particular features of the architectures. The CAD system under development includes: a tool for target architecture decomposition into primitive component; a tool for multilevel logic reduction for the primitive components; a tool for automatic gate placement within a primitive components; a tool for component placement within the target architecture; a high-level simulation tool; and a layout verification tool.