In this paper the design for a general purpose, high density, parallel CAM is presented. Many techniques that have been used in RAM design are applied to the development of a new architecture for a family of CAM chips. In addition several new techniques have been developed to solve some of the problems inherent in many previous CAM architectures. The high level block diagram is first introduced and the functional modes summarized. Two very dissimilar examples of applications of the CAM are then presented. Each component and its possible implementation in VLSI is described. The CAM design proposed is modular, so that larger CAMs can be built using the CAM chips as array slices with minimal additional external 'glue' logic.
|Original language||English (US)|
|Title of host publication||Unknown Host Publication Title|
|Editors||Charles E. Leiserson|
|Number of pages||21|
|Publication status||Published - Dec 1 1986|
All Science Journal Classification (ASJC) codes