Parameter variation tolerance and error resiliency: New design paradigm for the nanoscale era

Swaroop Ghosh, Kaushik Roy

Research output: Contribution to journalArticlepeer-review

138 Scopus citations

Abstract

Variations in process parameters affect the operation of integrated circuits (ICs) and pose a significant threat to the continued scaling of transistor dimensions. Such parameter variations, however, tend to affect logic and memory circuits in different ways. In logic, this fluctuation in device geometries might prevent them from meeting timing and power constraints and degrade the parametric yield. Memories, on the other hand, experience stability failures on account of such variations. Process limitations are not exhibited as physical disparities only; transistors experience temporal device degradation as well. Such issues are expected to further worsen with technology scaling. Resolving the problems of traditional Si-based technologies by employing non-Si alternatives may not present a viable solution; the non-Si miniature devices are expected to suffer the ill-effects of process/temporal variations as well. To circumvent these nonidealities, there is a need to design ICs that can adapt themselves to operate correctly under the presence of such inconsistencies. In this paper, we first provide an overview of the process variations and time-dependent degradation mechanisms. Next, we discuss the emerging paradigm of variation-tolerant adaptive design for both logic and memories. Interestingly, these resiliency techniques transcend several design abstraction levelswe present circuit and microarchitectural techniques to perform reliable computations in an unreliable environment.

Original languageEnglish (US)
Article number5551169
Pages (from-to)1718-1751
Number of pages34
JournalProceedings of the IEEE
Volume98
Issue number10
DOIs
StatePublished - Oct 2010

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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