Partial-product generation and addition for multiplication in FPGAS with 6-input LUTs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

Multiplication is the dominant operation for many applications implemented on field-programmable gate arrays (FPGAs). Although most current FPGA families have embedded hard multipliers, soft multipliers using lookup tables (LUTs) in the logic fabric remain important. This paper presents a novel circuit that combines radix-4 partial-product generation with addition (patent pending) and shows how it can be used to implement two's-complement multipliers. Single-cycle and pipelined designs for 8×8, 10×10, 12×12, 14×14 and 16×16 multipliers are compared to Xilinx LogiCORE IP multipliers. Proposed single-cycle parallel-tree multipliers use 35% to 45% fewer LUTs and have 9% to 22% less delay than LogiCORE IP multipliers. Proposed pipelined parallel-tree multipliers use 32% to 40% fewer LUTs than LogiCORE IP multipliers. Proposed parallel-array multipliers use even fewer LUTs than parallel-tree multipliers at the expense of increased delay.

Original languageEnglish (US)
Title of host publicationConference Record of the 48th Asilomar Conference on Signals, Systems and Computers
EditorsMichael B. Matthews
PublisherIEEE Computer Society
Pages1247-1251
Number of pages5
ISBN (Electronic)9781479982974
DOIs
StatePublished - Apr 24 2015
Event48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 - Pacific Grove, United States
Duration: Nov 2 2014Nov 5 2014

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
Volume2015-April
ISSN (Print)1058-6393

Other

Other48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015
Country/TerritoryUnited States
CityPacific Grove
Period11/2/1411/5/14

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

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