Path to a terabyte of on-chip memory for petabit per second bandwidth with < 5Watts of power

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Scopus citations

Abstract

We propose a path to achieve an ambitious target that has never been tried before: a terabyte of on-chip memory for petabit/second of bandwidth with < 5W of power. Conventional methodology of on-chip memory design is bottom up where the choice of bitcell topology and associated peripherals are predetermined. The resulting memory is sub-optimal and often suffers from high power and poor bandwidth. We approach this problem from top down where the capacity, bandwidth and power specifications guide the choice of bitcell. Our evaluation shows that domain wall memory (DWM) can be a potential technology that can meet TB capacity and Pb/s bandwidth with shoestring power budget. Categories and Subject Descriptors B.7.1Types & Design Styles - Advanced Technologies General Terms Performance, Design.

Original languageEnglish (US)
Title of host publicationProceedings of the 50th Annual Design Automation Conference, DAC 2013
DOIs
StatePublished - Jul 12 2013
Event50th Annual Design Automation Conference, DAC 2013 - Austin, TX, United States
Duration: May 29 2013Jun 7 2013

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other50th Annual Design Automation Conference, DAC 2013
CountryUnited States
CityAustin, TX
Period5/29/136/7/13

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

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    Ghosh, S. (2013). Path to a terabyte of on-chip memory for petabit per second bandwidth with < 5Watts of power. In Proceedings of the 50th Annual Design Automation Conference, DAC 2013 [145] (Proceedings - Design Automation Conference). https://doi.org/10.1145/2463209.2488913