Pen: Design and evaluation of partial-erase for 3D NAND-based high density SSDs

Chun Yi Liu, Jagadish B. Kotra, Myoungsoo Jung, Mahmut T. Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

3D NAND flash memories promise unprecedented flash storage capacities, which can be extremely important in certain application domains where both storage capacity and performance are first-class target metrics. However a block of 3D NAND flash contains many more pages than its 2D counterpart. This increased number of pages-per-block has numerous ramifications such as the longer erase latency, higher garbage collection costs, and increased write amplification factors, which can collectively prevent the 3D NAND flash products from becoming the mainstream in high-performance storage domain. In this paper, we introduce PEN, an architecture-level mechanism that enables partial-erase of flash blocks. Using our proposed partial-erase support, we also discuss how one can build a custom garbage collector for two types of flash translation layers (FTLs), namely, block-level FTL and hybrid FTL. Our experimental evaluations of PEN with a set of diverse real storage workloads indicate that the proposed approach can shorten the write latency by 44.3% and 47.9% for block-level FTL and hybrid FTL, respectively.

Original languageEnglish (US)
Title of host publicationProceedings of the 16th USENIX Conference on File and Storage Technologies, FAST 2018
PublisherUSENIX Association
Pages67-82
Number of pages16
ISBN (Electronic)9781931971423
StatePublished - Jan 1 2018
Event16th USENIX Conference on File and Storage Technologies, FAST 2018 - Oakland, United States
Duration: Feb 12 2018Feb 15 2018

Publication series

NameProceedings of the 16th USENIX Conference on File and Storage Technologies, FAST 2018

Conference

Conference16th USENIX Conference on File and Storage Technologies, FAST 2018
CountryUnited States
CityOakland
Period2/12/182/15/18

Fingerprint

Flash memory
Amplification
Costs

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Liu, C. Y., Kotra, J. B., Jung, M., & Kandemir, M. T. (2018). Pen: Design and evaluation of partial-erase for 3D NAND-based high density SSDs. In Proceedings of the 16th USENIX Conference on File and Storage Technologies, FAST 2018 (pp. 67-82). (Proceedings of the 16th USENIX Conference on File and Storage Technologies, FAST 2018). USENIX Association.
Liu, Chun Yi ; Kotra, Jagadish B. ; Jung, Myoungsoo ; Kandemir, Mahmut T. / Pen : Design and evaluation of partial-erase for 3D NAND-based high density SSDs. Proceedings of the 16th USENIX Conference on File and Storage Technologies, FAST 2018. USENIX Association, 2018. pp. 67-82 (Proceedings of the 16th USENIX Conference on File and Storage Technologies, FAST 2018).
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abstract = "3D NAND flash memories promise unprecedented flash storage capacities, which can be extremely important in certain application domains where both storage capacity and performance are first-class target metrics. However a block of 3D NAND flash contains many more pages than its 2D counterpart. This increased number of pages-per-block has numerous ramifications such as the longer erase latency, higher garbage collection costs, and increased write amplification factors, which can collectively prevent the 3D NAND flash products from becoming the mainstream in high-performance storage domain. In this paper, we introduce PEN, an architecture-level mechanism that enables partial-erase of flash blocks. Using our proposed partial-erase support, we also discuss how one can build a custom garbage collector for two types of flash translation layers (FTLs), namely, block-level FTL and hybrid FTL. Our experimental evaluations of PEN with a set of diverse real storage workloads indicate that the proposed approach can shorten the write latency by 44.3{\%} and 47.9{\%} for block-level FTL and hybrid FTL, respectively.",
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Liu, CY, Kotra, JB, Jung, M & Kandemir, MT 2018, Pen: Design and evaluation of partial-erase for 3D NAND-based high density SSDs. in Proceedings of the 16th USENIX Conference on File and Storage Technologies, FAST 2018. Proceedings of the 16th USENIX Conference on File and Storage Technologies, FAST 2018, USENIX Association, pp. 67-82, 16th USENIX Conference on File and Storage Technologies, FAST 2018, Oakland, United States, 2/12/18.

Pen : Design and evaluation of partial-erase for 3D NAND-based high density SSDs. / Liu, Chun Yi; Kotra, Jagadish B.; Jung, Myoungsoo; Kandemir, Mahmut T.

Proceedings of the 16th USENIX Conference on File and Storage Technologies, FAST 2018. USENIX Association, 2018. p. 67-82 (Proceedings of the 16th USENIX Conference on File and Storage Technologies, FAST 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Liu CY, Kotra JB, Jung M, Kandemir MT. Pen: Design and evaluation of partial-erase for 3D NAND-based high density SSDs. In Proceedings of the 16th USENIX Conference on File and Storage Technologies, FAST 2018. USENIX Association. 2018. p. 67-82. (Proceedings of the 16th USENIX Conference on File and Storage Technologies, FAST 2018).