Performance Analysis of Cluster-Based Multiprocessors

Prasant Mohapatra, Chita R. Das, Tse yun Feng

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

A queueing model for performance evaluation of cluster- based multiprocessors is proposed in this correspondence. Most system components are modeled as M / D / 1 / L queues to capture deterministic service time and finite buffer behavior. Various subsystems are analyzed independently and then integrated for the system level analysis. Average delay, throughput, and processor utilization are the performance parameters studied in this analysis. The analytical results are first validated via simulation. Next, several design alternatives are discussed using the model. These include the effect of buffer length and identification of bottleneck centers for various design configurations.

Original languageEnglish (US)
Pages (from-to)109-114
Number of pages6
JournalIEEE Transactions on Computers
Volume43
Issue number1
DOIs
StatePublished - Jan 1994

Fingerprint

Multiprocessor
Performance Analysis
Finite Buffer
Queueing Model
Queue
Performance Evaluation
Buffer
Subsystem
Throughput
Correspondence
Configuration
Alternatives
Simulation
Design
Model

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

Cite this

Mohapatra, Prasant ; Das, Chita R. ; Feng, Tse yun. / Performance Analysis of Cluster-Based Multiprocessors. In: IEEE Transactions on Computers. 1994 ; Vol. 43, No. 1. pp. 109-114.
@article{d2ec2d8f416f485fbe9c8d41042275c7,
title = "Performance Analysis of Cluster-Based Multiprocessors",
abstract = "A queueing model for performance evaluation of cluster- based multiprocessors is proposed in this correspondence. Most system components are modeled as M / D / 1 / L queues to capture deterministic service time and finite buffer behavior. Various subsystems are analyzed independently and then integrated for the system level analysis. Average delay, throughput, and processor utilization are the performance parameters studied in this analysis. The analytical results are first validated via simulation. Next, several design alternatives are discussed using the model. These include the effect of buffer length and identification of bottleneck centers for various design configurations.",
author = "Prasant Mohapatra and Das, {Chita R.} and Feng, {Tse yun}",
year = "1994",
month = "1",
doi = "10.1109/12.250615",
language = "English (US)",
volume = "43",
pages = "109--114",
journal = "IEEE Transactions on Computers",
issn = "0018-9340",
publisher = "IEEE Computer Society",
number = "1",

}

Performance Analysis of Cluster-Based Multiprocessors. / Mohapatra, Prasant; Das, Chita R.; Feng, Tse yun.

In: IEEE Transactions on Computers, Vol. 43, No. 1, 01.1994, p. 109-114.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Performance Analysis of Cluster-Based Multiprocessors

AU - Mohapatra, Prasant

AU - Das, Chita R.

AU - Feng, Tse yun

PY - 1994/1

Y1 - 1994/1

N2 - A queueing model for performance evaluation of cluster- based multiprocessors is proposed in this correspondence. Most system components are modeled as M / D / 1 / L queues to capture deterministic service time and finite buffer behavior. Various subsystems are analyzed independently and then integrated for the system level analysis. Average delay, throughput, and processor utilization are the performance parameters studied in this analysis. The analytical results are first validated via simulation. Next, several design alternatives are discussed using the model. These include the effect of buffer length and identification of bottleneck centers for various design configurations.

AB - A queueing model for performance evaluation of cluster- based multiprocessors is proposed in this correspondence. Most system components are modeled as M / D / 1 / L queues to capture deterministic service time and finite buffer behavior. Various subsystems are analyzed independently and then integrated for the system level analysis. Average delay, throughput, and processor utilization are the performance parameters studied in this analysis. The analytical results are first validated via simulation. Next, several design alternatives are discussed using the model. These include the effect of buffer length and identification of bottleneck centers for various design configurations.

UR - http://www.scopus.com/inward/record.url?scp=0028259439&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028259439&partnerID=8YFLogxK

U2 - 10.1109/12.250615

DO - 10.1109/12.250615

M3 - Article

AN - SCOPUS:0028259439

VL - 43

SP - 109

EP - 114

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 1

ER -