Performance analysis of combining multistage interconnection networks

Prasant Mohapatra, Sheldon Wong, Chitaranjan Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Concurrent access to a shared variable may cause network saturation in parallel computers. This problem, commonly termed as hot spot contention, can be alliviated by combining requests destined to the hot memory module. In this paper, we propose an analytical model to predict performance of combining multistage interconnection networks. The model considers realistic assumptions like finite length buffers in the switches, deterministic service time, finite degree of combining. Simulation results are used to validate the analytical model.

Original languageEnglish (US)
Title of host publicationProceedings of the 1994 International Conference on Parallel Processing, ICPP 1994
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)0849324939, 9780849324932
DOIs
StatePublished - Jan 1 1994
Event23rd International Conference on Parallel Processing, ICPP 1994 - Raleigh, NC, United States
Duration: Aug 15 1994Aug 19 1994

Publication series

NameProceedings of the International Conference on Parallel Processing
Volume1
ISSN (Print)0190-3918

Other

Other23rd International Conference on Parallel Processing, ICPP 1994
CountryUnited States
CityRaleigh, NC
Period8/15/948/19/94

All Science Journal Classification (ASJC) codes

  • Software
  • Mathematics(all)
  • Hardware and Architecture

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    Mohapatra, P., Wong, S., & Das, C. (1994). Performance analysis of combining multistage interconnection networks. In Proceedings of the 1994 International Conference on Parallel Processing, ICPP 1994 [4115684] (Proceedings of the International Conference on Parallel Processing; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICPP.1994.157