Performance and Energy Efficient Asymmetrically Reliable Caches for Multicore Architectures

Sanem Arslan, Haluk Rahmi Topcuoglu, Mahmut Kandemir, Oguz Tosun

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Modern architectures are increasingly susceptible to transient and permanent faults due to continuously decreasing transistor sizes and faster operating frequencies. The probability of soft error occurrence is relatively high on cache structures due to the large area of the logic compared to other parts. Applying fault tolerance unselectively for all caches has a significant overhead on performance and energy. In this study, we propose asymmetrically reliable caches aiming to provide required reliability using just enough extra hardware under the performance and energy constraints. In our framework, a chip multiprocessor consists of one reliability-aware core which has ECC protection on its data cache for critical data and a set of less reliable cores with unprotected data caches to map noncritical data. The experimental results for selected applications show that our proposed technique provides 21% better reliability for only 6% more energy consumption compared to traditional caches.

Original languageEnglish (US)
Title of host publicationProceedings - 2015 IEEE 29th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1025-1032
Number of pages8
ISBN (Electronic)0769555101, 9780769555102
DOIs
Publication statusPublished - Sep 29 2015
Event29th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2015 - Hyderabad, India
Duration: May 25 2015May 29 2015

Publication series

NameProceedings - 2015 IEEE 29th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2015

Other

Other29th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2015
CountryIndia
CityHyderabad
Period5/25/155/29/15

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All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Arslan, S., Topcuoglu, H. R., Kandemir, M., & Tosun, O. (2015). Performance and Energy Efficient Asymmetrically Reliable Caches for Multicore Architectures. In Proceedings - 2015 IEEE 29th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2015 (pp. 1025-1032). [7284423] (Proceedings - 2015 IEEE 29th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPDPSW.2015.113