Performance and power optimization through data compression in network-on-chip architectures

Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulosd, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar Iyer, Mazin S. Yousif, Chita R. Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

57 Scopus citations

Abstract

The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache banks interconnected through a packet-based Network-on-Chip (NoC) communication fabric. Thus, the NoC plays a critical role in optimizing the performance and power consumption of such non-uniform cache-based multicore architectures. While almost all prior NoC studies have focused on the design of router microarchitectures for achieving this goal, in this paper, we explore the role of data compression on NoC performance and energy behavior. In this context, we examine two different configurations that explore combinations of storage and communication compression: (1) Cache Compression (CC) and (2) Compression in the NIC (NC). We also address techniques to hide the decompression latency by overlapping with NoC communication latency. Our simulation results with a diverse set of scientific and commercial benchmark traces reveal that CC can provide up to 33% reduction in network latency and up to 23% power savings. Even in the case of NC - where the data is compressed only when passing through the NoC fabric of the NUCA architecture and stored uncompressed - performance and power savings of up to 32% and 21%, respectively, can be obtained. These performance benefits in the interconnect translate up to 17% reduction in CPI. These benefits are orthogonal to any router architecture and make a strong case for utilizing compression for optimizing the performance and power envelope of NoC architectures. In addition, the study demonstrates the criticality of designing faster routers in shaping the performance behavior.

Original languageEnglish (US)
Title of host publicationProceedings - International Symposium on High-Performance Computer Architecture
Pages215-225
Number of pages11
DOIs
StatePublished - Dec 24 2008
Event2008 IEEE 14th International Symposium on High Performance Computer Architecture, HPCA 2008 - Salt Lake City, UT, United States
Duration: Feb 16 2008Feb 20 2008

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other2008 IEEE 14th International Symposium on High Performance Computer Architecture, HPCA 2008
CountryUnited States
CitySalt Lake City, UT
Period2/16/082/20/08

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

Das, R., Mishra, A. K., Nicopoulosd, C., Park, D., Narayanan, V., Iyer, R., Yousif, M. S., & Das, C. R. (2008). Performance and power optimization through data compression in network-on-chip architectures. In Proceedings - International Symposium on High-Performance Computer Architecture (pp. 215-225). [4658641] (Proceedings - International Symposium on High-Performance Computer Architecture). https://doi.org/10.1109/HPCA.2008.4658641