Performance, energy, and reliability tradeoffs in replicating hot cache lines

W. Zhang, M. Kandemir, A. Sivasubramaniam, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

The importance of L1 data caches makes their performance, power consumption, and data integrity characteristics extremely critical in embedded systems design. We examine these issues in the context of a mechanism that tries to enhance data cache reliability by replicating cache lines (blocks) in active use. When replicating data cache lines, it is important to not evict other lines that may be needed or to not incur very high power consumption. We evaluate the tradeoffs between these three goals (reliability, energy, and performance) by modulating two important parameters, namely, the hot-block threshold and the dead-block threshold. We show that having a hot-block threshold in the range of 10-1000 cycles can provide good reliability characteristics, without compromising on performance or power. At the same time, our results indicate that one could use aggressive dead-block thresholds to provide leakage power savings without compromising on the performance and reliability characteristics. The results from this paper can be used to design power, performance, and reliability enhanced cache architectures.

Original languageEnglish (US)
Title of host publicationCASES 2003
Subtitle of host publicationInternational Conference on Compilers, Architecture, and Synthesis for Embedded Systems
PublisherAssociation for Computing Machinery (ACM)
Pages309-317
Number of pages9
ISBN (Print)1581136765, 9781581136760
DOIs
StatePublished - Jan 1 2003
EventCASES 2003: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems - San Jose, CA, United States
Duration: Oct 30 2003Nov 1 2003

Publication series

NameCASES 2003: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Other

OtherCASES 2003: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
CountryUnited States
CitySan Jose, CA
Period10/30/0311/1/03

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Zhang, W., Kandemir, M., Sivasubramaniam, A., & Irwin, M. J. (2003). Performance, energy, and reliability tradeoffs in replicating hot cache lines. In CASES 2003: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (pp. 309-317). (CASES 2003: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems). Association for Computing Machinery (ACM). https://doi.org/10.1145/951746.951750