Performance improvements through timing driven reconfiguration of black-boxes in platform FPGAs

Priya Sundararajan, Sridhar Krishnamurthy, N. Vijaykrishnan, Kamal Chaudhary, Rajeev Jayaraman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Platform FPGAs have introduced complex reconfigurable black-boxes for complete system on chip implementation. With rising expectations from these architectures there is a need to perform optimizations across the FPGA slice fabric and the newly introduced black boxes to maximize performance gains. In this paper, we discuss a timing driven reconfiguration technique to improve performance of DSP designs on platform FPGAs by (i) Optimal register placement algorithms within the DSP48 block and (ii) Timing driven mechanism to have maximal pipeline depth.

Original languageEnglish (US)
Title of host publication2006 IEEE International Systems-on-Chip Conference, SOC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages105-106
Number of pages2
ISBN (Print)0780397819, 9780780397811
DOIs
Publication statusPublished - Jan 1 2006
Event2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States
Duration: Sep 24 2006Sep 27 2006

Publication series

Name2006 IEEE International Systems-on-Chip Conference, SOC

Other

Other2006 IEEE International Systems-on-Chip Conference, SOC
CountryUnited States
CityAustin, TX
Period9/24/069/27/06

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Sundararajan, P., Krishnamurthy, S., Vijaykrishnan, N., Chaudhary, K., & Jayaraman, R. (2006). Performance improvements through timing driven reconfiguration of black-boxes in platform FPGAs. In 2006 IEEE International Systems-on-Chip Conference, SOC (pp. 105-106). [4063026] (2006 IEEE International Systems-on-Chip Conference, SOC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOCC.2006.283857