Performance model for a reconfigurable coprocessor

Syed S. Rizvi, Syed N. Hyder, Aasia Riasat

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents an analytical model for the performance of a generic reconfigurable coprocessor (RC) system. The system is characterized by a standard processor with a portion that is reconfigurable. We describe a general performance model for the speedup of a generic RC system. We demonstrate how different parameters of speedup model can affect the performance of reconfigurable system (RS). In addition, we implement our pre-developed speedup model for a system that allows preloading of the functional blocks (FB) into the reconfigurable hardware (RH). The redevelopment of speedup model with the consideration of preloading demonstrates some interesting results that can be used to improve the performance of RH with a coprocessor. Finally, we develop a performance model for a specific application. The application is characterized by a main iterative loop in which a core operation is to be defined in a FB. Our experiments show that the minimum and maximum speedup mainly depends on the probabilities of miss and hit for the FB that resides in the RH of a coprocessor. In addition, our simulation results for application specific model demonstrate how the probability of dependency degrades the achievable speedup.

Original languageEnglish (US)
Title of host publicationAdvances in Computer and Information Sciences and Engineering
Pages515-520
Number of pages6
DOIs
StatePublished - Dec 1 2008
Event2007 International Conference on Systems, Computing Sciences and Software Engineering, SCSS 2007, Part of the International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering, CISSE 2007 - Bridgeport, CT, United States
Duration: Dec 3 2007Dec 12 2007

Publication series

NameAdvances in Computer and Information Sciences and Engineering

Other

Other2007 International Conference on Systems, Computing Sciences and Software Engineering, SCSS 2007, Part of the International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering, CISSE 2007
CountryUnited States
CityBridgeport, CT
Period12/3/0712/12/07

All Science Journal Classification (ASJC) codes

  • Computer Science (miscellaneous)
  • Information Systems

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