Performance model for a reconfigurable coprocessor

This paper presents an analytical model for the performance of a generic reconfigurable coprocessor (RC) system. The system is characterized by a standard processor with a portion that is reconfigurable. We describe a general performance model for the speedup of a generic RC system. We demonstrate how different parameters of speedup model can affect the performance of reconfigurable system (RS). In addition, we implement our pre-developed speedup model for a system that allows preloading of the functional blocks (FB) into the reconfigurable hardware (RH). The redevelopment of speedup model with the consideration of preloading demonstrates some interesting results that can be used to improve the performance of RH with a coprocessor. Finally, we develop a performance model for a specific application. The application is characterized by a main iterative loop in which a core operation is to be defined in a FB. Our experiments show that the minimum and maximum speedup mainly depends on the probabilities of miss and hit for the FB that resides in the RH of a coprocessor. In addition, our simulation results for application specific model demonstrate how the probability of dependency degrades the achievable speedup.