Current switching speeds in CMOS technology have saturated since 2003 due to power constraints arising from the inability of line voltage to be further lowered in CMOS below about 1V. We are developing a novel switching technology based on piezoelectrically transducing the input or gate voltage into an acoustic wave which compresses a piezoresistive (PR) material forming the device channel. Under pressure the PR undergoes an insulator-to-metal transition which makes the channel conducting, turning on the device. A piezoelectric (PE) transducer material with a high piezoelectric coefficient, e.g. a domain-engineered relaxor piezoelectric, is needed to achieve low voltage operation. Suitable channel materials manifesting a pressure-induced metal-insulator transition can be found amongst rare earth chalcogenides, transition metal oxides, etc.. Mechanical requirements include a high PE/PR area ratio to step up pressure, a rigid surround material to constrain the PE and PR external boundaries normal to the strain axis, and a void space to enable free motion of the component side walls. Using static mechanical modeling and dynamic electroacoustic simulations, we optimize device structure and materials and predict performance. The device, termed a PiezoElectronic Transistor (PET) can be used to build complete logic circuits including inverters, flip-flops, and gates. This "Piezotronic" logic is predicted to have a combination of low power and high speed operation.