Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications

Niharika Thakuria; Atanu K. Saha; Sandeep K. Thirumala; Daniel Schulman; Saptarshi Das; Sumeet K. Gupta

doi:10.1109/DRC50226.2020.9135172

Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications

Niharika Thakuria, Atanu K. Saha, Sandeep K. Thirumala, Daniel Schulman, Saptarshi Das, Sumeet K. Gupta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

Among several non-volatile memories (NVMs), ferroelectric (FE) based memories show distinct advantages due to electric field ( E )-driven low-power write [1] - [2]. However, there are other concerns in FE based NVMs (such destructive read in FERAMs [3] , gate leakage in FEFETs with floating inter-layer metal (ILM) [5] and traps and depolarization fields in FEFETs without ILM [4] ). To overcome such issues while retaining the useful features of FE, we propose a Polarization-induced Strain coupled TMD FET (PS FET) [ Fig. 1(a) ] that features (a) polarization-based non-volatile bit-storage (b) E-driven write and (c) coupling of piezoelectricity with dynamic bandgap (EG) tuning of 2D Transition Metal Dichalcogenides (TMDs) for read [ Fig. 1(b) ].

Original language	English (US)
Title of host publication	2020 Device Research Conference, DRC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728170473
DOIs	https://doi.org/10.1109/DRC50226.2020.9135172
State	Published - Jun 2020
Event	2020 Device Research Conference, DRC 2020 - Columbus, United States Duration: Jun 21 2020 → Jun 24 2020

Publication series

Name	Device Research Conference - Conference Digest, DRC
Volume	2020-June
ISSN (Print)	1548-3770

Conference

Conference	2020 Device Research Conference, DRC 2020
Country/Territory	United States
City	Columbus
Period	6/21/20 → 6/24/20

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/DRC50226.2020.9135172

Cite this

Thakuria, N., Saha, A. K., Thirumala, S. K., Schulman, D., Das, S., & Gupta, S. K. (2020). Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications. In 2020 Device Research Conference, DRC 2020 [9135172] (Device Research Conference - Conference Digest, DRC; Vol. 2020-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DRC50226.2020.9135172

Thakuria, Niharika ; Saha, Atanu K. ; Thirumala, Sandeep K. ; Schulman, Daniel ; Das, Saptarshi ; Gupta, Sumeet K. / Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications. 2020 Device Research Conference, DRC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. (Device Research Conference - Conference Digest, DRC).

@inproceedings{9f20219ce40940ef89c572aa1efdd918,

title = "Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications",

abstract = "Among several non-volatile memories (NVMs), ferroelectric (FE) based memories show distinct advantages due to electric field ( E )-driven low-power write [1] - [2]. However, there are other concerns in FE based NVMs (such destructive read in FERAMs [3] , gate leakage in FEFETs with floating inter-layer metal (ILM) [5] and traps and depolarization fields in FEFETs without ILM [4] ). To overcome such issues while retaining the useful features of FE, we propose a Polarization-induced Strain coupled TMD FET (PS FET) [ Fig. 1(a) ] that features (a) polarization-based non-volatile bit-storage (b) E-driven write and (c) coupling of piezoelectricity with dynamic bandgap (EG) tuning of 2D Transition Metal Dichalcogenides (TMDs) for read [ Fig. 1(b) ].",

author = "Niharika Thakuria and Saha, {Atanu K.} and Thirumala, {Sandeep K.} and Daniel Schulman and Saptarshi Das and Gupta, {Sumeet K.}",

note = "Funding Information: Introduction: Among several non-volatile memories (NVMs), ferroelectric (FE) based memories show distinct advantages due to electric field (E)-driven low-power write [1-2]. However, there are other concerns in FE based NVMs (such destructive read in FERAMs [3], gate leakage in FEFETs with floating inter-layer metal (ILM) [5] and traps and depolarization fields in FEFETs without ILM [4]). To overcome such issues while retaining the useful features of FE, we propose a Polarization-induced Strain coupled TMD FET (PS FET) [Fig. 1(a)] that features (a) polarization-based non-volatile bit-storage (b) E-driven write and (c) coupling of piezoelectricity with dynamic bandgap (EG) tuning of 2D Transition Metal Dichalcogenides (TMDs) for read [Fig.1(b)]. PS FET Structure and Operation: PS FET is 4-terminal device comprising of drain (D), gate (G), source (S) and back (B) contacts [Fig. 1(a)]. The voltage across G and B controls a piezoelectric (PE) material (PZT-5H, which also exhibits ferroelectric properties). The G terminal also electrostatically controls the TMD channel (monolayer MoS2 in this work) [6]. Moreover, TMD channel properties are influenced by strain of the PE, as discussed subsequently. The bit is stored in the form of polarization (P) in PE, with +(-) P representing logic {\textquoteleft}1{\textquoteright} ({\textquoteleft}0{\textquoteright}). To write (switch P), we apply voltage across PE (VGB) such that |E| > coercive field of PE (EC) [7]. The polarity of VGB determines the logic state (±P) written in PS FET [Fig. 1(b)]. To sense the stored bit, we utilize P-induced strain in PE (SPE) [7]. SPE yields stress in PE (), which transduces as pressure in TMD (σTMD), leading to dynamic modulation in the bandgap (ΔEG) of TMD [8]. This tunes the drain current (IDS) leading to low/high resistance states (LRS/HRS) of PS FET. For +P, SPE > 0, ΔEG < 0 [Fig. 1(b)] and IDS = ILRS (high). Similarly, -P yields SPE < 0, ΔEG > 0 and low IDS = IHRS. To efficiently transduce to , we utilize the hammer and nail effect [9], wherein the area of TMD under the gate (ATMD) acts as the nail while PE serves as the hammer. For that, ATMD is designed to be smaller than the area of PE (APE) by increasing the PE dimensions along both length and width. Also, we choose metals with high stiffness for the nail, PE and source/drain contacts (e.g., Pd, Cr) to minimize loss of . Simulation Framework of PS FET: To analyze the proposed PS FET, we develop a simulation framework shown in Fig. 2. We model the P-E response of PZT-5H using Landau-Khalatnikov (LK) equation [10] [Fig. 2(a)] and calibrate it with experiment in [7] (Fig. 3). We utilize the S-E response from the same experiments [7] to extract piezoelectric coefficients (d33 and d31) of PZT-5H. These parameters are used to model pressure transduced to TMD () using COMSOL Multiphysics Suite. We simulate the full 3D structure of the proposed PS FETs (including the hammer and nail effect) in COMSOL and employ the strain-charge form of the constitutive equations for PE [Fig. 2(b)] with proper hard boundary conditions to obtain and . is converted to ΔEG and self-consistently coupled with the TMD charge/potential model based on [11] with parameters in [6, 15-16] [Fig. 2(c)] PS FET Characteristics: Our results from COMSOL simulations (Fig. 4) show that the hammer and nail effect cause to be boosted compared to [Fig. 4(a)], when the area of nail/TMD (ATMD) is lower than that of PE (APE), the hammer. The device parameter = / is a measure of this effect [9], where smaller is expected to provide larger . We observe ~12X increase in compared to at = 0.04 [Fig. 4(b)]. Optimization of the width of PE (WPE) can enable tuning of (Fig. 5), and hence and ΔEG. By increasing WPE from 90nm to 180nm, decreases from 0.07 to 0.03, leading to 1.78X increase in and ΔEG. To further explain the proposed read mechanism, we present the transfer (IDS-VGS) characteristics of PS FET for = 0.04 (Fig. 6). We apply gate voltage (VG) which is lower than coercive voltage (VC = 0.6V) of PZT-5H to ensure that the stored P state is undisturbed in this analysis. For +P, PS FET shows 2.3X higher IDS (ILRS) than standard 2D TMD FET while for –P, IDS is 3.4X lower (IHRS) due to strain driven ∓ΔEG. Based on the IDS-VGS characteristics, we identify that 0.3V < VGS < 0.4V provides optimal ILRS/IHRS, sufficient current necessary for read operation and ample read disturb margin (VC - VGS ~ 200mV). We choose VGS = VREAD = 0.35V that gives ILRS/IHRS ~ 8.2X. Note that ILRS/IHRS can be improved by material optimizations and device optimization (e.g. by reducing ), as discussed later. Access-Transistor-less PS FET Memory Array: Based on the unique read mechanism of PS FET, we propose an access-transistor-less memory array with decoupled read-write. The gate of PS FET is connected to the word line (WL), while the back terminal and drain are connected to the write bit-line (WBL) and read bit-line (RBL) respectively [Fig. 7(a)]. The write ports are connected in a cross-point fashion (and hence, the bits belonging to the same word are stored in different blocks, as in other cross point memories [12]). During write, WBL and WL of the accessed cell is such that |VGB| = VDD > VC appears across PE, resulting in P switching. For half-accessed cells [Fig. 7(b)], |VGB| = VDD/2 < VC prevents P switching. This design uses a positive-voltage-only biasing scheme (VWL = VDD, VWBL = 0 for +P write and VWBL=0, VWL = VDD for –P write). For read, we apply VREAD (based on Fig. 6) on WL and VDD on RBL of the accessed cell. The read current is sensed on RBL (shared along the column). No current flows through the half-accessed/unassessed cells as they have either their gate voltage or drain voltage or both = 0. PS FET shows a compact cell area in the range of 932 - 1832 ( is half the minimum feature size [13]) for 0.07 > > 0.03. [Fig. 8(a)]. A larger offers higher integration density, lower write energy and lower read power, albeit at the cost of lower ILRS/IHRS [Fig. 8(b)]. Summary and Discussions: We present a non-volatile memory utilizing polarization-based bit storage/switching and piezoelectricity induced dynamic bandgap modulation for bit sensing. The proposed PS FET NVM mitigates the limitations of FE-based memories (Fig. 9), while retaining their benefits of E-driven write. Specifically, it simultaneously exhibits the following features: (a) no effect of gate leakage on design margins because of the absence of floating metal (unlike FEFET with ILM), (b) non-destructive read (unlike FERAMs), (c) no effect of depolarization field on FE retention due to gate metal between PE and transistor (unlike FEFETs without ILM). However, PS FET exhibits trade-offs between distinguishability, energy and area, which needs proper device optimization (e.g. using ) and material selection. As an example, PS FET can be designed with PE based on Si-doped HfO2. While its elastic tensor components need further characterization (to enable the exploration of Si-doped HfO2 based PS FETs), recent experiments [14] have pointed to reasonable piezoelectric effects in Si-doped HfO2. Using Si-doped HfO2 in the design of PS FETs can potentially result in CMOS-compatibility, improved PE thickness scalability and better performance/energy-efficiency of PS FETs and their NVM arrays, beyond what we have presented in this work. References: [1] A. Chen ESSDERC, Sep. 2015 [2] M. Bibes, Nature Mater., Apr. 2012. [3] S.K. Gupta et al., ISQED, Mar. 2017 [4] T.P. Ma et al., IEEE EDL 2002 [5] A.I. Khan et al., IEEE TED, 2017 [6] M.P. Alveraz et. al, ACS Nano Lett., 2015 [7] M.H. Malakooti et al, APL, 2103 [8] A.P. Nayak et al, Nat. Comm. May 2014 [9] D.M. Newns et al, Adv.Funct. Mater, 2012 [10] A. Aziz et al, EDL 2016 [11] S. Suryavanshi et al, S2DS Model [12] Gupta et al., ISCAS, 2016 [13] Jan M Rabey, Digital Integrated Circuits [14] S Kirbach et al., IEEE Conf. of Nano. Tech, 2019 [15] Z. Yu et. al, Adv. Funct. Mater 2017, [16] C. D English, Nano Lett. 2016, [17] S.K. Thirumala, DRC, 2018. Acknowledgments: This research was supported, in part, by SRC/NSF funded E2CDA program (1640020) and Army Research Office (W911NF-19-1-0488).; 2020 Device Research Conference, DRC 2020 ; Conference date: 21-06-2020 Through 24-06-2020",

year = "2020",

month = jun,

doi = "10.1109/DRC50226.2020.9135172",

language = "English (US)",

series = "Device Research Conference - Conference Digest, DRC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 Device Research Conference, DRC 2020",

address = "United States",

}

Thakuria, N, Saha, AK, Thirumala, SK, Schulman, D, Das, S & Gupta, SK 2020, Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications. in 2020 Device Research Conference, DRC 2020., 9135172, Device Research Conference - Conference Digest, DRC, vol. 2020-June, Institute of Electrical and Electronics Engineers Inc., 2020 Device Research Conference, DRC 2020, Columbus, United States, 6/21/20. https://doi.org/10.1109/DRC50226.2020.9135172

Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications. / Thakuria, Niharika; Saha, Atanu K.; Thirumala, Sandeep K.; Schulman, Daniel; Das, Saptarshi; Gupta, Sumeet K.

2020 Device Research Conference, DRC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9135172 (Device Research Conference - Conference Digest, DRC; Vol. 2020-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications

AU - Thakuria, Niharika

AU - Saha, Atanu K.

AU - Thirumala, Sandeep K.

AU - Schulman, Daniel

AU - Das, Saptarshi

AU - Gupta, Sumeet K.

N1 - Funding Information: Introduction: Among several non-volatile memories (NVMs), ferroelectric (FE) based memories show distinct advantages due to electric field (E)-driven low-power write [1-2]. However, there are other concerns in FE based NVMs (such destructive read in FERAMs [3], gate leakage in FEFETs with floating inter-layer metal (ILM) [5] and traps and depolarization fields in FEFETs without ILM [4]). To overcome such issues while retaining the useful features of FE, we propose a Polarization-induced Strain coupled TMD FET (PS FET) [Fig. 1(a)] that features (a) polarization-based non-volatile bit-storage (b) E-driven write and (c) coupling of piezoelectricity with dynamic bandgap (EG) tuning of 2D Transition Metal Dichalcogenides (TMDs) for read [Fig.1(b)]. PS FET Structure and Operation: PS FET is 4-terminal device comprising of drain (D), gate (G), source (S) and back (B) contacts [Fig. 1(a)]. The voltage across G and B controls a piezoelectric (PE) material (PZT-5H, which also exhibits ferroelectric properties). The G terminal also electrostatically controls the TMD channel (monolayer MoS2 in this work) [6]. Moreover, TMD channel properties are influenced by strain of the PE, as discussed subsequently. The bit is stored in the form of polarization (P) in PE, with +(-) P representing logic ‘1’ (‘0’). To write (switch P), we apply voltage across PE (VGB) such that |E| > coercive field of PE (EC) [7]. The polarity of VGB determines the logic state (±P) written in PS FET [Fig. 1(b)]. To sense the stored bit, we utilize P-induced strain in PE (SPE) [7]. SPE yields stress in PE (), which transduces as pressure in TMD (σTMD), leading to dynamic modulation in the bandgap (ΔEG) of TMD [8]. This tunes the drain current (IDS) leading to low/high resistance states (LRS/HRS) of PS FET. For +P, SPE > 0, ΔEG < 0 [Fig. 1(b)] and IDS = ILRS (high). Similarly, -P yields SPE < 0, ΔEG > 0 and low IDS = IHRS. To efficiently transduce to , we utilize the hammer and nail effect [9], wherein the area of TMD under the gate (ATMD) acts as the nail while PE serves as the hammer. For that, ATMD is designed to be smaller than the area of PE (APE) by increasing the PE dimensions along both length and width. Also, we choose metals with high stiffness for the nail, PE and source/drain contacts (e.g., Pd, Cr) to minimize loss of . Simulation Framework of PS FET: To analyze the proposed PS FET, we develop a simulation framework shown in Fig. 2. We model the P-E response of PZT-5H using Landau-Khalatnikov (LK) equation [10] [Fig. 2(a)] and calibrate it with experiment in [7] (Fig. 3). We utilize the S-E response from the same experiments [7] to extract piezoelectric coefficients (d33 and d31) of PZT-5H. These parameters are used to model pressure transduced to TMD () using COMSOL Multiphysics Suite. We simulate the full 3D structure of the proposed PS FETs (including the hammer and nail effect) in COMSOL and employ the strain-charge form of the constitutive equations for PE [Fig. 2(b)] with proper hard boundary conditions to obtain and . is converted to ΔEG and self-consistently coupled with the TMD charge/potential model based on [11] with parameters in [6, 15-16] [Fig. 2(c)] PS FET Characteristics: Our results from COMSOL simulations (Fig. 4) show that the hammer and nail effect cause to be boosted compared to [Fig. 4(a)], when the area of nail/TMD (ATMD) is lower than that of PE (APE), the hammer. The device parameter = / is a measure of this effect [9], where smaller is expected to provide larger . We observe ~12X increase in compared to at = 0.04 [Fig. 4(b)]. Optimization of the width of PE (WPE) can enable tuning of (Fig. 5), and hence and ΔEG. By increasing WPE from 90nm to 180nm, decreases from 0.07 to 0.03, leading to 1.78X increase in and ΔEG. To further explain the proposed read mechanism, we present the transfer (IDS-VGS) characteristics of PS FET for = 0.04 (Fig. 6). We apply gate voltage (VG) which is lower than coercive voltage (VC = 0.6V) of PZT-5H to ensure that the stored P state is undisturbed in this analysis. For +P, PS FET shows 2.3X higher IDS (ILRS) than standard 2D TMD FET while for –P, IDS is 3.4X lower (IHRS) due to strain driven ∓ΔEG. Based on the IDS-VGS characteristics, we identify that 0.3V < VGS < 0.4V provides optimal ILRS/IHRS, sufficient current necessary for read operation and ample read disturb margin (VC - VGS ~ 200mV). We choose VGS = VREAD = 0.35V that gives ILRS/IHRS ~ 8.2X. Note that ILRS/IHRS can be improved by material optimizations and device optimization (e.g. by reducing ), as discussed later. Access-Transistor-less PS FET Memory Array: Based on the unique read mechanism of PS FET, we propose an access-transistor-less memory array with decoupled read-write. The gate of PS FET is connected to the word line (WL), while the back terminal and drain are connected to the write bit-line (WBL) and read bit-line (RBL) respectively [Fig. 7(a)]. The write ports are connected in a cross-point fashion (and hence, the bits belonging to the same word are stored in different blocks, as in other cross point memories [12]). During write, WBL and WL of the accessed cell is such that |VGB| = VDD > VC appears across PE, resulting in P switching. For half-accessed cells [Fig. 7(b)], |VGB| = VDD/2 < VC prevents P switching. This design uses a positive-voltage-only biasing scheme (VWL = VDD, VWBL = 0 for +P write and VWBL=0, VWL = VDD for –P write). For read, we apply VREAD (based on Fig. 6) on WL and VDD on RBL of the accessed cell. The read current is sensed on RBL (shared along the column). No current flows through the half-accessed/unassessed cells as they have either their gate voltage or drain voltage or both = 0. PS FET shows a compact cell area in the range of 932 - 1832 ( is half the minimum feature size [13]) for 0.07 > > 0.03. [Fig. 8(a)]. A larger offers higher integration density, lower write energy and lower read power, albeit at the cost of lower ILRS/IHRS [Fig. 8(b)]. Summary and Discussions: We present a non-volatile memory utilizing polarization-based bit storage/switching and piezoelectricity induced dynamic bandgap modulation for bit sensing. The proposed PS FET NVM mitigates the limitations of FE-based memories (Fig. 9), while retaining their benefits of E-driven write. Specifically, it simultaneously exhibits the following features: (a) no effect of gate leakage on design margins because of the absence of floating metal (unlike FEFET with ILM), (b) non-destructive read (unlike FERAMs), (c) no effect of depolarization field on FE retention due to gate metal between PE and transistor (unlike FEFETs without ILM). However, PS FET exhibits trade-offs between distinguishability, energy and area, which needs proper device optimization (e.g. using ) and material selection. As an example, PS FET can be designed with PE based on Si-doped HfO2. While its elastic tensor components need further characterization (to enable the exploration of Si-doped HfO2 based PS FETs), recent experiments [14] have pointed to reasonable piezoelectric effects in Si-doped HfO2. Using Si-doped HfO2 in the design of PS FETs can potentially result in CMOS-compatibility, improved PE thickness scalability and better performance/energy-efficiency of PS FETs and their NVM arrays, beyond what we have presented in this work. References: [1] A. Chen ESSDERC, Sep. 2015 [2] M. Bibes, Nature Mater., Apr. 2012. [3] S.K. Gupta et al., ISQED, Mar. 2017 [4] T.P. Ma et al., IEEE EDL 2002 [5] A.I. Khan et al., IEEE TED, 2017 [6] M.P. Alveraz et. al, ACS Nano Lett., 2015 [7] M.H. Malakooti et al, APL, 2103 [8] A.P. Nayak et al, Nat. Comm. May 2014 [9] D.M. Newns et al, Adv.Funct. Mater, 2012 [10] A. Aziz et al, EDL 2016 [11] S. Suryavanshi et al, S2DS Model [12] Gupta et al., ISCAS, 2016 [13] Jan M Rabey, Digital Integrated Circuits [14] S Kirbach et al., IEEE Conf. of Nano. Tech, 2019 [15] Z. Yu et. al, Adv. Funct. Mater 2017, [16] C. D English, Nano Lett. 2016, [17] S.K. Thirumala, DRC, 2018. Acknowledgments: This research was supported, in part, by SRC/NSF funded E2CDA program (1640020) and Army Research Office (W911NF-19-1-0488).

PY - 2020/6

Y1 - 2020/6

N2 - Among several non-volatile memories (NVMs), ferroelectric (FE) based memories show distinct advantages due to electric field ( E )-driven low-power write [1] - [2]. However, there are other concerns in FE based NVMs (such destructive read in FERAMs [3] , gate leakage in FEFETs with floating inter-layer metal (ILM) [5] and traps and depolarization fields in FEFETs without ILM [4] ). To overcome such issues while retaining the useful features of FE, we propose a Polarization-induced Strain coupled TMD FET (PS FET) [ Fig. 1(a) ] that features (a) polarization-based non-volatile bit-storage (b) E-driven write and (c) coupling of piezoelectricity with dynamic bandgap (EG) tuning of 2D Transition Metal Dichalcogenides (TMDs) for read [ Fig. 1(b) ].

AB - Among several non-volatile memories (NVMs), ferroelectric (FE) based memories show distinct advantages due to electric field ( E )-driven low-power write [1] - [2]. However, there are other concerns in FE based NVMs (such destructive read in FERAMs [3] , gate leakage in FEFETs with floating inter-layer metal (ILM) [5] and traps and depolarization fields in FEFETs without ILM [4] ). To overcome such issues while retaining the useful features of FE, we propose a Polarization-induced Strain coupled TMD FET (PS FET) [ Fig. 1(a) ] that features (a) polarization-based non-volatile bit-storage (b) E-driven write and (c) coupling of piezoelectricity with dynamic bandgap (EG) tuning of 2D Transition Metal Dichalcogenides (TMDs) for read [ Fig. 1(b) ].

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UR - http://www.scopus.com/inward/citedby.url?scp=85091340173&partnerID=8YFLogxK

U2 - 10.1109/DRC50226.2020.9135172

DO - 10.1109/DRC50226.2020.9135172

M3 - Conference contribution

AN - SCOPUS:85091340173

T3 - Device Research Conference - Conference Digest, DRC

BT - 2020 Device Research Conference, DRC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 Device Research Conference, DRC 2020

Y2 - 21 June 2020 through 24 June 2020

ER -

Thakuria N, Saha AK, Thirumala SK, Schulman D, Das S, Gupta SK. Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications. In 2020 Device Research Conference, DRC 2020. Institute of Electrical and Electronics Engineers Inc. 2020. 9135172. (Device Research Conference - Conference Digest, DRC). https://doi.org/10.1109/DRC50226.2020.9135172

Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications

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