Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network (Invited Paper)

Yuan Xie, Soumya Eachempati, Aditya Yanamandra, Vijaykrishnan Narayanan, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The gigahertz.frequency regime together with the rising delay of on-chip interconnect and increased device densities, has resulted in aggravating clock skew problem. Skew and power dissipation of clock distribution networks are key factors in determining the maximum attainable clock frequency as well as the chip power consumption. The traditional skew balancing schemes incur additional cost of increased area and power. In this paper, we propose a novel skew reduction mechanism using dissimilar interconnect materials for balancing the non-uniform loads in a clock network. Single walled carbon nanotube (SWCNT) bundles have been shown to have high electrical conductivity for future process technology nodes. We design a Htree clock network made up of both SWCNT bundles and copper interconnect at 22nm technology node. Our experiments show that such a network saves an average of65% in area and 22% ofpower over a pure copper distribution network.

Original languageEnglish (US)
Title of host publication2009 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2009
Pages51-56
Number of pages6
DOIs
StatePublished - Nov 11 2009
Event2009 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2009 - San Francisco, CA, United States
Duration: Jul 30 2009Jul 31 2009

Publication series

Name2009 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2009

Other

Other2009 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2009
CountryUnited States
CitySan Francisco, CA
Period7/30/097/31/09

All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Xie, Y., Eachempati, S., Yanamandra, A., Narayanan, V., & Irwin, M. J. (2009). Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network (Invited Paper). In 2009 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2009 (pp. 51-56). [5226352] (2009 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2009). https://doi.org/10.1109/NANOARCH.2009.5226352