Power and performance comparison of crossbars and buses as on-chip interconnect structures

Yan Zhang, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Traditionally, buses have been traditionally used as datapath interconnects because of their simplicity. Yet, as technology quickly scales down and the industry embraces systems-on-A-chip (SoC), the increasing global interconnect delay and chip power consumption become big concerns, and alternative datapath interconnect structures should be considered. This paper evaluates two datapath interconnection alternatives-full connection crossbars and multiple-input/output-port buses-At the transistor level and compares their power and delay performances. The results show that although a full connection crossbar consumes more energy per cycle and incurs larger delays than buses, crossbars consume less energy per data transfer when the number of input/output ports is small and the crossbar operates in full parallelism. This makes crossbars a good choice for connecting components and transferring parallel data in SoC designs.

Original languageEnglish (US)
Title of host publicationConference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages378-383
Number of pages6
Volume1
ISBN (Electronic)0780357000, 9780780357006
DOIs
StatePublished - Jan 1 1999
Event33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999 - Pacific Grove, United States
Duration: Oct 24 1999Oct 27 1999

Other

Other33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999
CountryUnited States
CityPacific Grove
Period10/24/9910/27/99

Fingerprint

Data transfer
Transistors
Electric power utilization
Industry

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

Cite this

Zhang, Y., & Irwin, M. J. (1999). Power and performance comparison of crossbars and buses as on-chip interconnect structures. In Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers (Vol. 1, pp. 378-383). [832356] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ACSSC.1999.832356
Zhang, Yan ; Irwin, Mary Jane. / Power and performance comparison of crossbars and buses as on-chip interconnect structures. Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers. Vol. 1 Institute of Electrical and Electronics Engineers Inc., 1999. pp. 378-383
@inproceedings{721210f5e12f4a80aad3810a158347a0,
title = "Power and performance comparison of crossbars and buses as on-chip interconnect structures",
abstract = "Traditionally, buses have been traditionally used as datapath interconnects because of their simplicity. Yet, as technology quickly scales down and the industry embraces systems-on-A-chip (SoC), the increasing global interconnect delay and chip power consumption become big concerns, and alternative datapath interconnect structures should be considered. This paper evaluates two datapath interconnection alternatives-full connection crossbars and multiple-input/output-port buses-At the transistor level and compares their power and delay performances. The results show that although a full connection crossbar consumes more energy per cycle and incurs larger delays than buses, crossbars consume less energy per data transfer when the number of input/output ports is small and the crossbar operates in full parallelism. This makes crossbars a good choice for connecting components and transferring parallel data in SoC designs.",
author = "Yan Zhang and Irwin, {Mary Jane}",
year = "1999",
month = "1",
day = "1",
doi = "10.1109/ACSSC.1999.832356",
language = "English (US)",
volume = "1",
pages = "378--383",
booktitle = "Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

Zhang, Y & Irwin, MJ 1999, Power and performance comparison of crossbars and buses as on-chip interconnect structures. in Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers. vol. 1, 832356, Institute of Electrical and Electronics Engineers Inc., pp. 378-383, 33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999, Pacific Grove, United States, 10/24/99. https://doi.org/10.1109/ACSSC.1999.832356

Power and performance comparison of crossbars and buses as on-chip interconnect structures. / Zhang, Yan; Irwin, Mary Jane.

Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers. Vol. 1 Institute of Electrical and Electronics Engineers Inc., 1999. p. 378-383 832356.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Power and performance comparison of crossbars and buses as on-chip interconnect structures

AU - Zhang, Yan

AU - Irwin, Mary Jane

PY - 1999/1/1

Y1 - 1999/1/1

N2 - Traditionally, buses have been traditionally used as datapath interconnects because of their simplicity. Yet, as technology quickly scales down and the industry embraces systems-on-A-chip (SoC), the increasing global interconnect delay and chip power consumption become big concerns, and alternative datapath interconnect structures should be considered. This paper evaluates two datapath interconnection alternatives-full connection crossbars and multiple-input/output-port buses-At the transistor level and compares their power and delay performances. The results show that although a full connection crossbar consumes more energy per cycle and incurs larger delays than buses, crossbars consume less energy per data transfer when the number of input/output ports is small and the crossbar operates in full parallelism. This makes crossbars a good choice for connecting components and transferring parallel data in SoC designs.

AB - Traditionally, buses have been traditionally used as datapath interconnects because of their simplicity. Yet, as technology quickly scales down and the industry embraces systems-on-A-chip (SoC), the increasing global interconnect delay and chip power consumption become big concerns, and alternative datapath interconnect structures should be considered. This paper evaluates two datapath interconnection alternatives-full connection crossbars and multiple-input/output-port buses-At the transistor level and compares their power and delay performances. The results show that although a full connection crossbar consumes more energy per cycle and incurs larger delays than buses, crossbars consume less energy per data transfer when the number of input/output ports is small and the crossbar operates in full parallelism. This makes crossbars a good choice for connecting components and transferring parallel data in SoC designs.

UR - http://www.scopus.com/inward/record.url?scp=0033345970&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033345970&partnerID=8YFLogxK

U2 - 10.1109/ACSSC.1999.832356

DO - 10.1109/ACSSC.1999.832356

M3 - Conference contribution

VL - 1

SP - 378

EP - 383

BT - Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Zhang Y, Irwin MJ. Power and performance comparison of crossbars and buses as on-chip interconnect structures. In Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers. Vol. 1. Institute of Electrical and Electronics Engineers Inc. 1999. p. 378-383. 832356 https://doi.org/10.1109/ACSSC.1999.832356