Power-aware designers at odds with power grid designers?

Mary Jane Irwin

Research output: Contribution to journalReview article

Abstract

The article discusses the issue of power consumption of on-chip power grid circuits. Runtime solutions that have emerged include clock gating, dynamic voltage and frequency scaling, adaptive body biasing, use of sleep transistors, and transitions to doze states. However, some of the solutions to constrain power consumption make the on-chip power grid designer's job even more difficult. Power-aware designers are now promoting self-timed systems as a solution to the power crisis.

Original languageEnglish (US)
Pages (from-to)120
Number of pages1
JournalIEEE Design and Test of Computers
Volume20
Issue number3
StatePublished - 2003

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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