The article discusses the issue of power consumption of on-chip power grid circuits. Runtime solutions that have emerged include clock gating, dynamic voltage and frequency scaling, adaptive body biasing, use of sleep transistors, and transitions to doze states. However, some of the solutions to constrain power consumption make the on-chip power grid designer's job even more difficult. Power-aware designers are now promoting self-timed systems as a solution to the power crisis.
|Original language||English (US)|
|Number of pages||1|
|Journal||IEEE Design and Test of Computers|
|State||Published - 2003|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering