Power-aware partitioned cache architectures

S. Kim, N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, M. J. Irwin, E. Geethanjali

Research output: Contribution to conferencePaperpeer-review

30 Scopus citations


This paper focuses on partitioning the cache resources architecturally for energy and energy-delay optimizations. Specifically, we investigate ways of splitting the cache into several smaller units, each of which is a cache by itself (called subcache). Subcache architectures not only reduce the per-access energy costs but can potentially improve the locality behavior as well. We present a unified framework for designing, implementing and evaluating different subcache architectures. Different techniques for data placement, subcache prediction, and selective probing are proposed and evaluated using a diverse set of applications. The results show that intelligent subcache mechanisms proposed in this paper are effective.

Original languageEnglish (US)
Number of pages4
StatePublished - 2001
EventInternational Symposium on Low Electronics and Design (ISLPED'01) - Huntington Beach, CA, United States
Duration: Aug 6 2001Aug 7 2001


OtherInternational Symposium on Low Electronics and Design (ISLPED'01)
Country/TerritoryUnited States
CityHuntington Beach, CA

All Science Journal Classification (ASJC) codes

  • Engineering(all)


Dive into the research topics of 'Power-aware partitioned cache architectures'. Together they form a unique fingerprint.

Cite this