Power-Delay Characteristics of CMOS Adders

Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin

Research output: Contribution to journalArticlepeer-review

27 Scopus citations

Abstract

An approach to designing CMOS adders for both high speed and low power is presented by analyzing the performance of three types of adders-linear time adders, logN time adders and constant time adders. The representative adders used are a ripple carry adder, a blocked carry lookahead adder and several signed-digit adders, respectively. Some of the tradeoffs that are possible during the logic design of an adder to improve its power-delay product are identified. An effective way of improving the speed of a circuit is by transistor sizing which unfortunately increases power dissipation to a large extent. It is shown that by sizing transistors judiciously it is possible to gain significant speed improvements at the cost of only a slight increase in power and hence a better power-delay product. Perflex, an in-house performance driven layout generator, is used to systematically eenerate sized layouts.

Original languageEnglish (US)
Pages (from-to)377-381
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume2
Issue number3
DOIs
StatePublished - Sep 1994

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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