Power protocol: Reducing power dissipation on off-chip data buses

K. Basu, A. Choudhary, J. Pisharath, Mahmut Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

38 Scopus citations


Power consumption is becoming increasingly important for both embedded and high-performance systems. Off-chip data buses can be a major power consumer. In this paper we present a strategy called "power protocol" that tries to reduce the dynamic power dissipation on off-chip data buses. To accomplish this, our strategy reduces the number of bus lines that need to be activated for data transfer by employing a small cache (called "value cache") at each side of the off-chip data bus. These value caches keep track of the data values that have recently been transmitted over the bus. The entries in these caches are constructed in such a way that the contents of both the value caches are the same all the time. When a data value needs to be transmitted over the bus, we first check whether it is in the value cache of the sender. If it is, we transmit only the index of the data (i.e., its value cache address) instead of the actual data value and, the other side (receiver) can determine the data value by using this index and its value cache. Our experimental results using a set of fifteen benchmark codes from embedded systems domain show that power protocol is very effective in practice, and reduces the bit switching activity on the data bus by as much as 70.7% (with a value cache of 128 entries). We also present results from an implementation that combines our strategy with 1-to-2 encoding, a popular bus encoding strategy for low power. Our results indicate that this combined optimization strategy reduces bit switching activity by 67.8% on the average (across all benchmarks). These reductions in bit switching activity lead to more than 7% reduction on overall system energy on the average for a value cache of 256 entries. We also study the sensitivity of our savings to the value cache capacity and data cache capacity.

Original languageEnglish (US)
Title of host publicationProceedings - 35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002
PublisherIEEE Computer Society
Number of pages11
ISBN (Electronic)0769518591
StatePublished - Jan 1 2002
Event35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002 - Istanbul, Turkey
Duration: Nov 18 2002Nov 22 2002

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451


Other35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


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