Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect

S. Eachempati, Vijaykrishnan Narayanan, A. Nieuwoudt, Y. Massoud

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

The authors investigate the performance and reliability of routing architectures in field programmable gate arrays (FPGA) that utilise bundles of single-walled carbon nanotubes (SWCNT) as wires in the FPGA interconnect fabric in future process technologies here. To leverage the performance advantages of nanotube-based interconnect, we explore several important aspects of the FPGA routing architecture including the wire length segmentation distribution and the switch/connection block configurations. The authors also investigate the impact of statistical variations in interconnect properties on FPGA timing yield. The results demonstrate that FPGAs utilising SWCNT bundle interconnect can achieve up to a 54 improvement in area-delay product over the best performing architecture with standard copper interconnect in 22nm process technology. Furthermore, FPGAs implemented using SWCNT-based interconnect can provide a superior performance-yield trade-off of up to 43 over FPGAs implemented using traditional copper interconnect in future process technologies.

Original languageEnglish (US)
Pages (from-to)64-75
Number of pages12
JournalIET Circuits, Devices and Systems
Volume3
Issue number2
DOIs
StatePublished - Apr 20 2009

Fingerprint

Field programmable gate arrays (FPGA)
Carbon nanotubes
Single-walled carbon nanotubes (SWCN)
Wire
Copper
Nanotubes
Switches

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

@article{77415731c182455599c36be7ac3abdc6,
title = "Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect",
abstract = "The authors investigate the performance and reliability of routing architectures in field programmable gate arrays (FPGA) that utilise bundles of single-walled carbon nanotubes (SWCNT) as wires in the FPGA interconnect fabric in future process technologies here. To leverage the performance advantages of nanotube-based interconnect, we explore several important aspects of the FPGA routing architecture including the wire length segmentation distribution and the switch/connection block configurations. The authors also investigate the impact of statistical variations in interconnect properties on FPGA timing yield. The results demonstrate that FPGAs utilising SWCNT bundle interconnect can achieve up to a 54 improvement in area-delay product over the best performing architecture with standard copper interconnect in 22nm process technology. Furthermore, FPGAs implemented using SWCNT-based interconnect can provide a superior performance-yield trade-off of up to 43 over FPGAs implemented using traditional copper interconnect in future process technologies.",
author = "S. Eachempati and Vijaykrishnan Narayanan and A. Nieuwoudt and Y. Massoud",
year = "2009",
month = "4",
day = "20",
doi = "10.1049/iet-cds.2008.0149",
language = "English (US)",
volume = "3",
pages = "64--75",
journal = "IET Circuits, Devices and Systems",
issn = "1751-858X",
publisher = "Institution of Engineering and Technology",
number = "2",

}

Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect. / Eachempati, S.; Narayanan, Vijaykrishnan; Nieuwoudt, A.; Massoud, Y.

In: IET Circuits, Devices and Systems, Vol. 3, No. 2, 20.04.2009, p. 64-75.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect

AU - Eachempati, S.

AU - Narayanan, Vijaykrishnan

AU - Nieuwoudt, A.

AU - Massoud, Y.

PY - 2009/4/20

Y1 - 2009/4/20

N2 - The authors investigate the performance and reliability of routing architectures in field programmable gate arrays (FPGA) that utilise bundles of single-walled carbon nanotubes (SWCNT) as wires in the FPGA interconnect fabric in future process technologies here. To leverage the performance advantages of nanotube-based interconnect, we explore several important aspects of the FPGA routing architecture including the wire length segmentation distribution and the switch/connection block configurations. The authors also investigate the impact of statistical variations in interconnect properties on FPGA timing yield. The results demonstrate that FPGAs utilising SWCNT bundle interconnect can achieve up to a 54 improvement in area-delay product over the best performing architecture with standard copper interconnect in 22nm process technology. Furthermore, FPGAs implemented using SWCNT-based interconnect can provide a superior performance-yield trade-off of up to 43 over FPGAs implemented using traditional copper interconnect in future process technologies.

AB - The authors investigate the performance and reliability of routing architectures in field programmable gate arrays (FPGA) that utilise bundles of single-walled carbon nanotubes (SWCNT) as wires in the FPGA interconnect fabric in future process technologies here. To leverage the performance advantages of nanotube-based interconnect, we explore several important aspects of the FPGA routing architecture including the wire length segmentation distribution and the switch/connection block configurations. The authors also investigate the impact of statistical variations in interconnect properties on FPGA timing yield. The results demonstrate that FPGAs utilising SWCNT bundle interconnect can achieve up to a 54 improvement in area-delay product over the best performing architecture with standard copper interconnect in 22nm process technology. Furthermore, FPGAs implemented using SWCNT-based interconnect can provide a superior performance-yield trade-off of up to 43 over FPGAs implemented using traditional copper interconnect in future process technologies.

UR - http://www.scopus.com/inward/record.url?scp=64549151995&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=64549151995&partnerID=8YFLogxK

U2 - 10.1049/iet-cds.2008.0149

DO - 10.1049/iet-cds.2008.0149

M3 - Article

AN - SCOPUS:64549151995

VL - 3

SP - 64

EP - 75

JO - IET Circuits, Devices and Systems

JF - IET Circuits, Devices and Systems

SN - 1751-858X

IS - 2

ER -