Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd

Swaroop Ghosh, Pooja Batra, Keejong Kim, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Designing low power pipelines in modern high performance microprocessors is becoming a challenging task due to increasing process parameter fluctuation associated with the scaled devices. Conventional low power design techniques typically make the critical paths of pipeline stages sensitive to parametric variations, degrading the yield. We implement a low-power and robust pipeline design methodology which is suitable for aggressive voltage scaling while maintaining high frequency operations. This is achieved by isolating the critical paths; making them predictable (by design) and ensuring they are activated rarely. At scaled supply (with frequency unchanged), any possible delay errors (under 1-cycle operations) are predicted ahead in time and avoided by adaptively stretching the clock period to 2-cycles. The test-chip implementing the design methodology for a two-stage pipeline in 130nm process shows 40% power savings with only 13% performance loss (due to adaptive clock stretching operations) and ∼9.4% area overhead.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages733-736
Number of pages4
ISBN (Electronic)1424407869, 9781424407866
DOIs
StatePublished - Jan 1 2007
Event29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States
Duration: Sep 16 2007Sep 19 2007

Publication series

NameProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Conference

Conference29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
CountryUnited States
CitySan Jose
Period9/16/079/19/07

Fingerprint

Pipelines
Stretching
Clocks
Microprocessor chips

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Ghosh, S., Batra, P., Kim, K., & Roy, K. (2007). Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (pp. 733-736). [4405835] (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405835
Ghosh, Swaroop ; Batra, Pooja ; Kim, Keejong ; Roy, Kaushik. / Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd. Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. pp. 733-736 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007).
@inproceedings{eafb54d3c5e74832a6ed71d37dba5468,
title = "Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd",
abstract = "Designing low power pipelines in modern high performance microprocessors is becoming a challenging task due to increasing process parameter fluctuation associated with the scaled devices. Conventional low power design techniques typically make the critical paths of pipeline stages sensitive to parametric variations, degrading the yield. We implement a low-power and robust pipeline design methodology which is suitable for aggressive voltage scaling while maintaining high frequency operations. This is achieved by isolating the critical paths; making them predictable (by design) and ensuring they are activated rarely. At scaled supply (with frequency unchanged), any possible delay errors (under 1-cycle operations) are predicted ahead in time and avoided by adaptively stretching the clock period to 2-cycles. The test-chip implementing the design methodology for a two-stage pipeline in 130nm process shows 40{\%} power savings with only 13{\%} performance loss (due to adaptive clock stretching operations) and ∼9.4{\%} area overhead.",
author = "Swaroop Ghosh and Pooja Batra and Keejong Kim and Kaushik Roy",
year = "2007",
month = "1",
day = "1",
doi = "10.1109/CICC.2007.4405835",
language = "English (US)",
series = "Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "733--736",
booktitle = "Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007",
address = "United States",

}

Ghosh, S, Batra, P, Kim, K & Roy, K 2007, Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd. in Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007., 4405835, Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, Institute of Electrical and Electronics Engineers Inc., pp. 733-736, 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007, San Jose, United States, 9/16/07. https://doi.org/10.1109/CICC.2007.4405835

Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd. / Ghosh, Swaroop; Batra, Pooja; Kim, Keejong; Roy, Kaushik.

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. p. 733-736 4405835 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd

AU - Ghosh, Swaroop

AU - Batra, Pooja

AU - Kim, Keejong

AU - Roy, Kaushik

PY - 2007/1/1

Y1 - 2007/1/1

N2 - Designing low power pipelines in modern high performance microprocessors is becoming a challenging task due to increasing process parameter fluctuation associated with the scaled devices. Conventional low power design techniques typically make the critical paths of pipeline stages sensitive to parametric variations, degrading the yield. We implement a low-power and robust pipeline design methodology which is suitable for aggressive voltage scaling while maintaining high frequency operations. This is achieved by isolating the critical paths; making them predictable (by design) and ensuring they are activated rarely. At scaled supply (with frequency unchanged), any possible delay errors (under 1-cycle operations) are predicted ahead in time and avoided by adaptively stretching the clock period to 2-cycles. The test-chip implementing the design methodology for a two-stage pipeline in 130nm process shows 40% power savings with only 13% performance loss (due to adaptive clock stretching operations) and ∼9.4% area overhead.

AB - Designing low power pipelines in modern high performance microprocessors is becoming a challenging task due to increasing process parameter fluctuation associated with the scaled devices. Conventional low power design techniques typically make the critical paths of pipeline stages sensitive to parametric variations, degrading the yield. We implement a low-power and robust pipeline design methodology which is suitable for aggressive voltage scaling while maintaining high frequency operations. This is achieved by isolating the critical paths; making them predictable (by design) and ensuring they are activated rarely. At scaled supply (with frequency unchanged), any possible delay errors (under 1-cycle operations) are predicted ahead in time and avoided by adaptively stretching the clock period to 2-cycles. The test-chip implementing the design methodology for a two-stage pipeline in 130nm process shows 40% power savings with only 13% performance loss (due to adaptive clock stretching operations) and ∼9.4% area overhead.

UR - http://www.scopus.com/inward/record.url?scp=62949100523&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=62949100523&partnerID=8YFLogxK

U2 - 10.1109/CICC.2007.4405835

DO - 10.1109/CICC.2007.4405835

M3 - Conference contribution

AN - SCOPUS:62949100523

T3 - Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

SP - 733

EP - 736

BT - Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Ghosh S, Batra P, Kim K, Roy K. Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc. 2007. p. 733-736. 4405835. (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). https://doi.org/10.1109/CICC.2007.4405835