Process variation aware parallelization strategies for MPSoCs

Suresh Srinivasan, Raghavan Ramadoss, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Scaling of microprocessors is aggravating the gap between design and manufacturing expectations. Such variations may lead to manufacturing of processors cores with frequencies lower or higher than their expected frequencies. In particular, with the rapid advent of Multiprocessor System on Chips (MPSoC), such manufacturing uncertainties may lead to significant variations in the operating frequencies of different processor cores on the same chip. In this work, we demonstrate that traditional load balanced parallelization schemes need to be revisited to account for such variations. Specifically, we highlight the need for tuning the degree of parallelization and non-uniform workload generation to achieve lower power consumption in next generation MPSoCs.

Original languageEnglish (US)
Title of host publication2006 IEEE International Systems-on-Chip Conference, SOC
Pages179-182
Number of pages4
DOIs
StatePublished - Dec 1 2007
Event2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States
Duration: Sep 24 2006Sep 27 2006

Publication series

Name2006 IEEE International Systems-on-Chip Conference, SOC

Other

Other2006 IEEE International Systems-on-Chip Conference, SOC
CountryUnited States
CityAustin, TX
Period9/24/069/27/06

Fingerprint

Microprocessor chips
Electric power utilization
Tuning
Uncertainty
System-on-chip

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Srinivasan, S., Ramadoss, R., & Narayanan, V. (2007). Process variation aware parallelization strategies for MPSoCs. In 2006 IEEE International Systems-on-Chip Conference, SOC (pp. 179-182). [4063045] (2006 IEEE International Systems-on-Chip Conference, SOC). https://doi.org/10.1109/SOCC.2006.283876
Srinivasan, Suresh ; Ramadoss, Raghavan ; Narayanan, Vijaykrishnan. / Process variation aware parallelization strategies for MPSoCs. 2006 IEEE International Systems-on-Chip Conference, SOC. 2007. pp. 179-182 (2006 IEEE International Systems-on-Chip Conference, SOC).
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Srinivasan, S, Ramadoss, R & Narayanan, V 2007, Process variation aware parallelization strategies for MPSoCs. in 2006 IEEE International Systems-on-Chip Conference, SOC., 4063045, 2006 IEEE International Systems-on-Chip Conference, SOC, pp. 179-182, 2006 IEEE International Systems-on-Chip Conference, SOC, Austin, TX, United States, 9/24/06. https://doi.org/10.1109/SOCC.2006.283876

Process variation aware parallelization strategies for MPSoCs. / Srinivasan, Suresh; Ramadoss, Raghavan; Narayanan, Vijaykrishnan.

2006 IEEE International Systems-on-Chip Conference, SOC. 2007. p. 179-182 4063045 (2006 IEEE International Systems-on-Chip Conference, SOC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Srinivasan S, Ramadoss R, Narayanan V. Process variation aware parallelization strategies for MPSoCs. In 2006 IEEE International Systems-on-Chip Conference, SOC. 2007. p. 179-182. 4063045. (2006 IEEE International Systems-on-Chip Conference, SOC). https://doi.org/10.1109/SOCC.2006.283876