Process variation aware parallelization strategies for MPSoCs

Suresh Srinivasan, Raghavan Ramadoss, N. Vijaykrishnan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Scaling of microprocessors is aggravating the gap between design and manufacturing expectations. Such variations may lead to manufacturing of processors cores with frequencies lower or higher than their expected frequencies. In particular, with the rapid advent of Multiprocessor System on Chips (MPSoC), such manufacturing uncertainties may lead to significant variations in the operating frequencies of different processor cores on the same chip. In this work, we demonstrate that traditional load balanced parallelization schemes need to be revisited to account for such variations. Specifically, we highlight the need for tuning the degree of parallelization and non-uniform workload generation to achieve lower power consumption in next generation MPSoCs.

Original languageEnglish (US)
Title of host publication2006 IEEE International Systems-on-Chip Conference, SOC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages179-182
Number of pages4
ISBN (Print)0780397819, 9780780397811
DOIs
StatePublished - Jan 1 2006
Event2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States
Duration: Sep 24 2006Sep 27 2006

Publication series

Name2006 IEEE International Systems-on-Chip Conference, SOC

Other

Other2006 IEEE International Systems-on-Chip Conference, SOC
CountryUnited States
CityAustin, TX
Period9/24/069/27/06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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