Properties of Si / SiO2 interfaces in vertical trench MOSFETs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations


We report on the study of the Si/SiO2 interface of vertical U-shaped trench-gated n+ - polycrystalline Si / oxide / Si (UMOS) capacitor gate structure using capacitance-deep level transient spectroscopy (c-DLTS) and capacitance-voltage (CV). The oxide of a UMOS capacitor is three-dimensional- thermally-grown at different temperature 900°C - 1175°C, on sidewall and base of a reactive-ion etched silicon surface. High-density mid-gap Si/SiO 2 interfacial traps (∼1011 eV-1 cm -2) are observed with both holes and electron trapping. The amphoteric nature of traps is argued to arise from the Pb- dangling Si bond defect center. Moreover, a study of UMOSFET channel region using constant-amplitude charge pumping (CP), measurements coupled with electrical stressing of the gate oxide in the Fowler-Nordheim (FN) regime, have shown that the oxide edge adjacent to the drain and the oxide/silicon interface therein are the most susceptible regions to damage. SEM revealed non-uniformity in oxide thickness. Finally, enhanced UMOSFETS channel characteristics are observed for rounded-comer trench-bottom geometry in contrast with sharp-corner trench-bottom geometry.

Original languageEnglish (US)
Title of host publicationExtended Abstracts of the Sixth International Workshop on Junction Technology, IWJT '06
Number of pages4
StatePublished - 2006
EventExtended Abstracts of the 6th International Workshop on Junction Technology, IWJT '06 - Shanghai, China
Duration: May 15 2006May 16 2006


OtherExtended Abstracts of the 6th International Workshop on Junction Technology, IWJT '06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Surfaces and Interfaces


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