Quantifying and optimizing the impact of victim cache line selection in manycore systems

Mahmut Kandemir, Wei Ding, Diana Guttman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In both architecture and software, the main goal of data locality-oriented optimizations has always been 'minimizing the number of cache misses' (especially, costly last-level cache misses). However, this paper shows that other metrics such as the distance between the last-level cache and memory controller as well as the memory queuing latency can play an equally important role, as far as application performance is concerned. Focusing on a large set of multithreaded applications, we first show that the last-level cache 'write backs' (memory writes due to displacement of a victim block from the last-level cache) can exhibit significant latencies as well as variances, and then make a case for 'relaxing' the strict LRU policy to save (write back) cycles in both the on-chip network and memory queues. Specifically, we explore novel architecture-level schemes that optimize on-chip network latency, memory queuing latency or both, of the write back messages, by carefully selecting the victim block to write back at the time of cache replacement. Our extensive experimental evaluations using 15 multithreaded applications and a cycle-accurate simulation infrastructure clearly demonstrate that this tradeoffs (between cache hit rate and on-chip network/memory queuing latency) pays off in most of the cases, leading to about 12.2% execution time improvement and 14.9% energy savings, in our default 64-core system with 6 memory controllers.

Original languageEnglish (US)
Title of host publicationProceedings - 2014 22nd Annual IEEE International Symposium on Modeling, Analysis and Simulation of Computer, and Telecommunication Systems, MASCOTS 2014
PublisherIEEE Computer Society
Pages385-394
Number of pages10
EditionFebruary
ISBN (Electronic)9781479956104
DOIs
StatePublished - Feb 5 2015
Event2014 22nd Annual IEEE International Symposium on Modeling, Analysis and Simulation of Computer, and Telecommunication Systems, MASCOTS 2014 - Paris, France
Duration: Sep 9 2014Sep 11 2014

Publication series

NameProceedings - IEEE Computer Society's Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, MASCOTS
NumberFebruary
Volume2015-February
ISSN (Print)1526-7539

Other

Other2014 22nd Annual IEEE International Symposium on Modeling, Analysis and Simulation of Computer, and Telecommunication Systems, MASCOTS 2014
CountryFrance
CityParis
Period9/9/149/11/14

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Networks and Communications
  • Software
  • Modeling and Simulation

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  • Cite this

    Kandemir, M., Ding, W., & Guttman, D. (2015). Quantifying and optimizing the impact of victim cache line selection in manycore systems. In Proceedings - 2014 22nd Annual IEEE International Symposium on Modeling, Analysis and Simulation of Computer, and Telecommunication Systems, MASCOTS 2014 (February ed., pp. 385-394). [7033676] (Proceedings - IEEE Computer Society's Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, MASCOTS; Vol. 2015-February, No. February). IEEE Computer Society. https://doi.org/10.1109/MASCOTS.2014.54