Reactive tiling

Jithendra Srinivas, Wei Ding, Mahmut Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

To fully exploit the power of emerging multicore architectures, managing shared resources (i.e., caches) across applications and over time is critical. However, to our knowledge, most prior efforts view this problem from the OS/hardware side, and do not consider whether applications themselves can also participate in this process of managing shared resources. In this paper, we show how an application can react to OS/hardware-based resource management decisions by adapting itself (called reactive application), with the goal of maximizing the utilization of the shared resources allocated to it. Specifically, we present a framework that can generate code for adaptive (reactive) tiling, and propose an execution model in which a reactive application can react to the modulations in its cache space allocations to prevent its performance from degrading. One can expect two potential benefits from this approach. First, matching tile size to available cache capacity dynamically (during execution) improves performance of the target application. Second and equally important, better utilization of shared cache space reduces pressure on other applications (co-runners) that execute concurrently with the target application. Our experimental results show that the proposed scheme improves the performance of applications (over the best static tiles) by 8.4%, on average, when using synthetic cache allocations. Further with dynamic cache allocations determined by the utility-based cache partitioning (a state-of-the-art cache partitioning scheme), it improves performance of a set of eleven HPC applications by 11.3%.

Original languageEnglish (US)
Title of host publicationProceedings of the 2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages91-102
Number of pages12
ISBN (Electronic)9781479981618
DOIs
StatePublished - Mar 3 2015
Event2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015 - San Francisco, United States
Duration: Feb 7 2015Feb 11 2015

Publication series

NameProceedings of the 2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015

Other

Other2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015
CountryUnited States
CitySan Francisco
Period2/7/152/11/15

Fingerprint

Tiling
Cache
Tile
Resources
Partitioning
Hardware
Target
Resource Management
Modulation
Experimental Results

All Science Journal Classification (ASJC) codes

  • Applied Mathematics
  • Control and Optimization
  • Computer Science Applications
  • Computational Theory and Mathematics

Cite this

Srinivas, J., Ding, W., & Kandemir, M. (2015). Reactive tiling. In Proceedings of the 2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015 (pp. 91-102). [7054190] (Proceedings of the 2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CGO.2015.7054190
Srinivas, Jithendra ; Ding, Wei ; Kandemir, Mahmut. / Reactive tiling. Proceedings of the 2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 91-102 (Proceedings of the 2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015).
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Srinivas, J, Ding, W & Kandemir, M 2015, Reactive tiling. in Proceedings of the 2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015., 7054190, Proceedings of the 2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015, Institute of Electrical and Electronics Engineers Inc., pp. 91-102, 2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015, San Francisco, United States, 2/7/15. https://doi.org/10.1109/CGO.2015.7054190

Reactive tiling. / Srinivas, Jithendra; Ding, Wei; Kandemir, Mahmut.

Proceedings of the 2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 91-102 7054190 (Proceedings of the 2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - To fully exploit the power of emerging multicore architectures, managing shared resources (i.e., caches) across applications and over time is critical. However, to our knowledge, most prior efforts view this problem from the OS/hardware side, and do not consider whether applications themselves can also participate in this process of managing shared resources. In this paper, we show how an application can react to OS/hardware-based resource management decisions by adapting itself (called reactive application), with the goal of maximizing the utilization of the shared resources allocated to it. Specifically, we present a framework that can generate code for adaptive (reactive) tiling, and propose an execution model in which a reactive application can react to the modulations in its cache space allocations to prevent its performance from degrading. One can expect two potential benefits from this approach. First, matching tile size to available cache capacity dynamically (during execution) improves performance of the target application. Second and equally important, better utilization of shared cache space reduces pressure on other applications (co-runners) that execute concurrently with the target application. Our experimental results show that the proposed scheme improves the performance of applications (over the best static tiles) by 8.4%, on average, when using synthetic cache allocations. Further with dynamic cache allocations determined by the utility-based cache partitioning (a state-of-the-art cache partitioning scheme), it improves performance of a set of eleven HPC applications by 11.3%.

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M3 - Conference contribution

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Srinivas J, Ding W, Kandemir M. Reactive tiling. In Proceedings of the 2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 91-102. 7054190. (Proceedings of the 2015 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2015). https://doi.org/10.1109/CGO.2015.7054190