Recent developments in performance driven Steiner routing: an overview

M. Borah, R. M. Owens, M. J. Irwin

Research output: Contribution to journalConference article

Abstract

The contribution of interconnect delay to the stage delay of a circuit is increasing with scaling of the minimum feature size. At larger feature size the interconnect delay contribution was small and the driver resistance was very large compared to wire resistance. Consequently, a simple lumped model was sufficient for evaluating and optimizing circuit delay. However, with sub-micron processes, the contribution of interconnect delay dominates the stage delay and the wire resistance becomes noticeable, making the interconnect delay dependent on the routing topology. Hence it is becoming necessary to use a more accurate model for estimating and optimizing interconnect delay. This paper surveys the recent advancements in techniques for generating on-chip interconnect topology for optimizing circuit performance.

Original languageEnglish (US)
Pages (from-to)137-142
Number of pages6
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
StatePublished - Jan 1 1996
EventProceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI - Ames, IA, USA
Duration: Mar 22 1996Mar 23 1996

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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