TY - GEN
T1 - Reconfigurable 60-GHz Radar Transmitter SoC with Broadband Frequency Tripler in 45nm SOI CMOS
AU - Lee, Wooram
AU - Dinc, Tolga
AU - Valdes-Garcia, Alberto
N1 - Funding Information:
ACKNOWLEDGEMENT This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA). The views, opinions and/or findings expressed are those of the authors should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government. The authors thank M. Ferriss, B. Sadhu, M. Yeck, and H. Liu for technical discussions and support and Daniel Friedman for management support.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/6
Y1 - 2019/6
N2 - A reconfigurable 60-GHz radar transmitter with a broadband frequency tripler is proposed to support CW/FMCW, pulse, and PMCW radar waveforms from a single front-end. The proposed IC consists of a wide-band frequency tripler, a two-stage driver, two power mixers with baseband circuitry and serial I/O circuitry. The IC measurements in CW mode operation show an output power of 12.8 dBm (average) and 14.7 dBm (peak) from 54 GHz to 67 GHz with harmonic suppression greater than 27 dB. Pulse and PMCW mode operations are also demonstrated to generate short pulses with the minimum pulse width of 25 ps corresponding to 40 GHz signal bandwidth and 10-Gb/s PRBS modulated signals, respectively. Fabricated in a 45-nm CMOS SOI process, the IC consumes 0.51 W and occupies an active area of 1.95 mm2 excluding pads.
AB - A reconfigurable 60-GHz radar transmitter with a broadband frequency tripler is proposed to support CW/FMCW, pulse, and PMCW radar waveforms from a single front-end. The proposed IC consists of a wide-band frequency tripler, a two-stage driver, two power mixers with baseband circuitry and serial I/O circuitry. The IC measurements in CW mode operation show an output power of 12.8 dBm (average) and 14.7 dBm (peak) from 54 GHz to 67 GHz with harmonic suppression greater than 27 dB. Pulse and PMCW mode operations are also demonstrated to generate short pulses with the minimum pulse width of 25 ps corresponding to 40 GHz signal bandwidth and 10-Gb/s PRBS modulated signals, respectively. Fabricated in a 45-nm CMOS SOI process, the IC consumes 0.51 W and occupies an active area of 1.95 mm2 excluding pads.
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U2 - 10.1109/RFIC.2019.8701736
DO - 10.1109/RFIC.2019.8701736
M3 - Conference contribution
AN - SCOPUS:85072245243
T3 - Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
SP - 43
EP - 46
BT - 2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2019
Y2 - 2 June 2019 through 4 June 2019
ER -