Reconfigurable ferroelectric transistor-part II

Application in low-power nonvolatile memories

Sandeep Krishna Thirumala, Sumeet Kumar Gupta

Research output: Contribution to journalArticle

Abstract

In Part I, we proposed reconfigurable ferroelectric transistors (R-FEFETs) with a unique property of dynamic modulation between the volatile (logic) and nonvolatile (memory) modes of operation with the help of a control signal. They showcase excellent robustness in the presence of gate leakage with larger hysteresis in the nonvolatile mode with respect to ferroelectric FETs (FEFETs) and higher ON current in the volatile mode compared with standard FETs. Using the unique attributes of R-FEFETs presented in Part I, we explain the dynamics of transition between various modes of operation for circuit-level applications in this paper. We propose a 3T nonvolatile memory design that offers significant power savings over FEFET-based memories by virtue of the control terminal. Our analysis shows that the proposed R-FEFET memory exhibits 55% lower write power and 37%-72% lower read power at iso access time and 33% lower area compared with a recently proposed standard FEFET-based memory.

Original languageEnglish (US)
Article number8710628
Pages (from-to)2780-2788
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume66
Issue number6
DOIs
StatePublished - Jun 1 2019

Fingerprint

Ferroelectric materials
Transistors
Data storage equipment
Field effect transistors
Hysteresis
Modulation
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Thirumala, Sandeep Krishna ; Gupta, Sumeet Kumar. / Reconfigurable ferroelectric transistor-part II : Application in low-power nonvolatile memories. In: IEEE Transactions on Electron Devices. 2019 ; Vol. 66, No. 6. pp. 2780-2788.
@article{65f7e8febea24091b6008d954e8a7905,
title = "Reconfigurable ferroelectric transistor-part II: Application in low-power nonvolatile memories",
abstract = "In Part I, we proposed reconfigurable ferroelectric transistors (R-FEFETs) with a unique property of dynamic modulation between the volatile (logic) and nonvolatile (memory) modes of operation with the help of a control signal. They showcase excellent robustness in the presence of gate leakage with larger hysteresis in the nonvolatile mode with respect to ferroelectric FETs (FEFETs) and higher ON current in the volatile mode compared with standard FETs. Using the unique attributes of R-FEFETs presented in Part I, we explain the dynamics of transition between various modes of operation for circuit-level applications in this paper. We propose a 3T nonvolatile memory design that offers significant power savings over FEFET-based memories by virtue of the control terminal. Our analysis shows that the proposed R-FEFET memory exhibits 55{\%} lower write power and 37{\%}-72{\%} lower read power at iso access time and 33{\%} lower area compared with a recently proposed standard FEFET-based memory.",
author = "Thirumala, {Sandeep Krishna} and Gupta, {Sumeet Kumar}",
year = "2019",
month = "6",
day = "1",
doi = "10.1109/TED.2019.2912562",
language = "English (US)",
volume = "66",
pages = "2780--2788",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "6",

}

Reconfigurable ferroelectric transistor-part II : Application in low-power nonvolatile memories. / Thirumala, Sandeep Krishna; Gupta, Sumeet Kumar.

In: IEEE Transactions on Electron Devices, Vol. 66, No. 6, 8710628, 01.06.2019, p. 2780-2788.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Reconfigurable ferroelectric transistor-part II

T2 - Application in low-power nonvolatile memories

AU - Thirumala, Sandeep Krishna

AU - Gupta, Sumeet Kumar

PY - 2019/6/1

Y1 - 2019/6/1

N2 - In Part I, we proposed reconfigurable ferroelectric transistors (R-FEFETs) with a unique property of dynamic modulation between the volatile (logic) and nonvolatile (memory) modes of operation with the help of a control signal. They showcase excellent robustness in the presence of gate leakage with larger hysteresis in the nonvolatile mode with respect to ferroelectric FETs (FEFETs) and higher ON current in the volatile mode compared with standard FETs. Using the unique attributes of R-FEFETs presented in Part I, we explain the dynamics of transition between various modes of operation for circuit-level applications in this paper. We propose a 3T nonvolatile memory design that offers significant power savings over FEFET-based memories by virtue of the control terminal. Our analysis shows that the proposed R-FEFET memory exhibits 55% lower write power and 37%-72% lower read power at iso access time and 33% lower area compared with a recently proposed standard FEFET-based memory.

AB - In Part I, we proposed reconfigurable ferroelectric transistors (R-FEFETs) with a unique property of dynamic modulation between the volatile (logic) and nonvolatile (memory) modes of operation with the help of a control signal. They showcase excellent robustness in the presence of gate leakage with larger hysteresis in the nonvolatile mode with respect to ferroelectric FETs (FEFETs) and higher ON current in the volatile mode compared with standard FETs. Using the unique attributes of R-FEFETs presented in Part I, we explain the dynamics of transition between various modes of operation for circuit-level applications in this paper. We propose a 3T nonvolatile memory design that offers significant power savings over FEFET-based memories by virtue of the control terminal. Our analysis shows that the proposed R-FEFET memory exhibits 55% lower write power and 37%-72% lower read power at iso access time and 33% lower area compared with a recently proposed standard FEFET-based memory.

UR - http://www.scopus.com/inward/record.url?scp=85065902925&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85065902925&partnerID=8YFLogxK

U2 - 10.1109/TED.2019.2912562

DO - 10.1109/TED.2019.2912562

M3 - Article

VL - 66

SP - 2780

EP - 2788

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 6

M1 - 8710628

ER -