Reducing Code Size Through Address Register Assignment

G. Chen, M. Kandemir, M. J. Irwin, J. Ramanujam

Research output: Contribution to journalArticle

6 Scopus citations

Abstract

In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance, since studies of programs have shown that instructions that manipulate address registers constitute a significant portion of the overall instruction count (up to 55%). This work presents a compiler-based optimization strategy to “reduce the code size in embedded systems.” Our strategy maximizes the use of indirect addressing modes with postincrement/decrement capabilities available in DSP processors. These modes can be exploited by ensuring that successive references to variables access consecutive memory locations. To achieve this spatial locality, our approach uses both access pattern modification (program code restructuring) and memory storage reordering (data layout restructuring). Experimental results on a set of benchmark codes show the effectiveness of our solution and indicate that our approach outperforms the previous approaches to the problem. In addition to resulting in significant reductions in instruction memory (storage) requirements, the proposed technique improves execution time.

Original languageEnglish (US)
Pages (from-to)225-258
Number of pages34
JournalACM Transactions on Embedded Computing Systems
Volume5
Issue number1
DOIs
StatePublished - Feb 1 2006

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture

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