Reducing leakage energy in FPGAs using region-constrained placement

A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwirn, T. Tuan

Research output: Contribution to conferencePaper

97 Scopus citations

Abstract

FPGAs are being increasingly used in a wide variety of applications. While power optimization has been only of secondary importance in many FPGA applications, growing importance of leakage in FPGAs designed in 90nm and below makes it imperative to treat power optimization as a first class citizen. In this paper, we propose a leakage-saving technique for FPGAs that involves dividing the FPGA fabric into small regions and switching on/off the power supply to each region using a sleep transistor in order to conserve leakage energy. Specifically, the regions not used by the placed design are supply gated. Next, we present a new placement strategy to increase the number of regions that can be supply gated. Finally, the supply gating technique is extended to exploit idleness in different parts of the same design during different time periods. Our experiments with different region sizes using various commercial and academic designs indicate that the proposed optimization outperforms conventional placement, and reduces leakage power consumption significantly.

Original languageEnglish (US)
Pages51-58
Number of pages8
DOIs
StatePublished - 2004
EventACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004 - Monterey, CA., United States
Duration: Feb 22 2004Feb 24 2004

Other

OtherACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004
CountryUnited States
CityMonterey, CA.
Period2/22/042/24/04

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

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    Gayasen, A., Tsai, Y., Vijaykrishnan, N., Kandemir, M., Irwirn, M. J., & Tuan, T. (2004). Reducing leakage energy in FPGAs using region-constrained placement. 51-58. Paper presented at ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004, Monterey, CA., United States. https://doi.org/10.1145/968280.968289