Reducing memory requirements through task recomputation in embedded multi-CPU systems

H. Koc, S. Tosun, O. Ozturk, M. Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

As embedded applications are processing increasingly larger data sets, keeping their memory space consumptions under control is becoming a very pressing issue. Observing this, several prior efforts have considered memory space reduction techniques (in both hardware and software) based on data compression and lifetime-based memory recycling (garbage collection). In this work, we propose and evaluate an alternate approach to memory space saving in multi-CPU embedded systems such as chip multiprocessors. The unique characteristic of our approach is that it recomputes the results of select tasks in a given task graph (which represents the application), instead of storing these results in memory and accessing them from there as needed.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Pages448-449
Number of pages2
DOIs
StatePublished - Oct 9 2006
EventIEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 - Klarlsruhe, Germany
Duration: Mar 2 2006Mar 3 2006

Publication series

NameProceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Volume2006

Other

OtherIEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
CountryGermany
CityKlarlsruhe
Period3/2/063/3/06

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Koc, H., Tosun, S., Ozturk, O., & Kandemir, M. (2006). Reducing memory requirements through task recomputation in embedded multi-CPU systems. In Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 (pp. 448-449). [1602490] (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006; Vol. 2006). https://doi.org/10.1109/ISVLSI.2006.77