Reducing NoC energy consumption through compiler-directed channel voltage scaling

Guangyu Chen, Feihui Li, Mahmut Kandemir, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

While scalable NoC (Network-on-Chip) based communication architectures have clear advantages over long point-to-point communication channels, their power consumption can be very high. In contrast to most of the existing hardware-based efforts on NoC power optimization, this paper proposes a compiler-directed approach where the compiler decides the appropriate voltage/frequency levels to be used for each communication channel in the NoC. Our approach builds and operates on a novel graph based representation of a parallel program and has been implemented within an optimizing compiler and tested using 12 embedded benchmarks. Our experiments indicate that the proposed approach behaves better - from both performance and power perspectives - than a hardware-based scheme and the energy savings it achieves are very close to the savings that could be obtained from an optimal, but hypothetical voltage/frequency scaling scheme.

Original languageEnglish (US)
Title of host publicationPLDI 2006 - Proceedings of the 2006 ACM SIGPLAN Conference on Programming Language Design and Implementation
Pages193-203
Number of pages11
StatePublished - Jul 24 2006
EventPLDI 2006 - 2006 ACM SIGPLAN Conference on Programming Language Design and Implementation - Ottawa, ON, Canada
Duration: Jun 10 2006Jun 16 2006

Publication series

NameProceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)
Volume2006

Other

OtherPLDI 2006 - 2006 ACM SIGPLAN Conference on Programming Language Design and Implementation
CountryCanada
CityOttawa, ON
Period6/10/066/16/06

All Science Journal Classification (ASJC) codes

  • Software

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