Reducing NoC energy consumption through compiler-directed channel voltage scaling

Guangyu Chen, Feihui Li, Mahmut Kandemir, Mary Jane Irwin

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

While scalable NoC (Network-on-Chip) based communication architectures have clear advantages over long point-to-point communication channels, their power consumption can be very high. In contrast to most of the existing hardware-based efforts on NoC power optimization, this paper proposes a compiler-directed approach where the compiler decides the appropriate voltage/frequency levels to be used for each communication channel in the NoC. Our approach builds and operates on a novel graph based representation of a parallel program and has been implemented within an optimizing compiler and tested using 12 embedded benchmarks. Our experiments indicate that the proposed approach behaves better -from both performance and power perspectives - than a hardware-based scheme and the energy savings it achieves are very close to the savings that could be obtained from an optimal, but hypothetical voltage/frequency scaling scheme.

Original languageEnglish (US)
Pages (from-to)193-203
Number of pages11
JournalACM SIGPLAN Notices
Volume41
Issue number6
DOIs
StatePublished - Jun 26 2006

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design

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