Reducing non-deterministic loads in low-power caches via early cache set resolution

Soontae Kim, Vijaykrishnan Narayanan, Mary Jane Irwin

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of non-determinism in cache access latency. Due to this additional latency, instructions dependent on a load speculatively issued must be squashed and re-issued as they will not have the correct data in time. Our experiments show that there is a large performance degradation and associated dynamic energy wastage due to these effects of instruction squashing. To address this problem, we propose an early cache set resolution scheme. Our experimental evaluation shows that this technique is quite effective in mitigating the problem.

Original languageEnglish (US)
Pages (from-to)293-301
Number of pages9
JournalMicroprocessors and Microsystems
Volume31
Issue number5
DOIs
StatePublished - Aug 1 2007

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence

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